AT43USB325 datasheet(20/109 Pages) ATMEL

20 / 109 page

3355C–USB–4/05

AT43USB325

Functional Description

4.1

On-chip Power Supply

The AT43USB325 contains two on-chip power supplies that generate 3.3V with a capacity of 30

mA each from the 5V power input. The on-chip power supplies are intended to supply the

AT43USB325 internal circuit and the 1.5K pull-up resistor only and should not be used for other

purposes. External 2.2 µF filter capacitors are required at the power supply outputs, CEXT1 and

CEXT2. The internal power supplies can be disabled as described in the next paragraph.

The user should be careful when the GPIO pins are required to supply high-load currents. If the

application requires that the GPIO supply currents beyond the capability of the on-chip power

supply, the AT43USB325 should be supplied by an external 3.3V power supply. In this case, the

5V V

CC power supply pin should be left unconnected and the 3.3V power supplied to the chip

through the CEXT1 and CEXT2 pins.

4.2

I/O Pin Characteristics

The I/O pins of the AT43USB325 should not be directly connected to voltages less than V

SS or

more than the voltage at the CEXT pins. If it is necessary to violate this rule, insert a series resis-

tor between the I/O pin and the source of the external signal source that limits the current into

the I/O pin to less than 2 mA. Under no circumstance should the external voltage exceed 5.5V.

To do so will put the chip under excessive stress.

4.3

Oscillator and PLL

All clock signals required to operate the AT43USB325 are derived from an on-chip oscillator. To

reduce EMI and power dissipation, the oscillator is designed to operate with a 6 MHz crystal. An

on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface

Engine. In the suspended state, the oscillator circuitry is turned off.

The oscillator of the AT43USB325 is a special, low-drive type, designed to work with most crys-

tals without any external components. The crystal must be of the parallel resonance type

requiring a load capacitance of about 10 pF. If the crystal requires a higher value capacitance,

external capacitors can be added to the two terminals of the crystal and ground to meet the

required value. To assure quick start-up, a crystal with a high Q, or low ESR, should be used. To

meet the USB hub frequency accuracy and stability requirements for hubs, the crystal should

have an accuracy and stability of better than 100 PPM. The use of a ceramic resonator in place

of the crystal is not recommended because a resonator would not have the necessary frequency

accuracy and stability.

The clock can also be externally sourced. In this case, connect the clock source to the XTAL1

pin, while leaving XTAL2 pin floating. The switching level at the OSC1 pin can be as low as

0.47V and a CMOS device is required to drive this pin to maintain good noise margins at the low

switching level.

For proper operation of the PLL, an external RC filter consisting of a series RC network of 100

Ω

and 0.1 µF in parallel with a 0.01 µF capacitor must be connected from the LFT pin to V

SS. Use

only high-quality ceramic capacitors.

AT43USB325 Datasheet(PDF) 20 Page - ATMEL Corporation

AT43USB325 Datasheet(HTML) 20 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL