AT43USB325 datasheet(27/109 Pages) ATMEL

27 / 109 page

3355C–USB–4/05

AT43USB325

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT43USB325 and always read as zero.

4.9.2

General Interrupt Flag Register – GIFR

• Bit 7 – INTF1: External Interrupt Flag1

When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-

bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at

address $004. The flag is cleared when the interrupt routine is executed. Alternatively, the flag

can be cleared by writing a logical one to it.

• Bit 6 – INTF0: Interrupt Flag0 (Suspend/Resume Interrupt Flag)

When an event on the INT0 (that is, a USB event-related interrupt) triggers an interrupt request,

INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU

will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is

executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT43USB325 and always read as zero.

4.9.3

Timer/Counter Interrupt Mask Register – TIMSK

• Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is

executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the

Timer/Counter Interrupt Flag Register (TIFR).

• Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector

$004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is

set in the TIFR.

• Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector

Bit

543

$3A ($5A)

INTF1

INT F0

–

GIFR

Read/Write

R/W

Initial Value

Bit

210

$39 ($59)

TOIE1

OCIE1A

OCIE1NB

–

TICIE1

–

TOIE0

–

TIMSK

Read/Write

R/W

Initial Value

AT43USB325 Datasheet(PDF) 27 Page - ATMEL Corporation

AT43USB325 Datasheet(HTML) 27 Page - ATMEL Corporation

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