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Status Registers ST0 and ST1

4-16

Table 4–2. Bit Fields of Status Registers ST0 and ST1

Name

Description

ARB

Auxiliary register pointer buffer. Whenever the auxiliary register pointer (ARP) is loaded, the

previous ARP value is copied to the ARB, except during an LST (load status register) instruction.

When the ARB is loaded by an LST instruction, the same value is also copied to the ARP.

ARP

Auxiliary register pointer. This 3-bit field selects which auxiliary register (AR) to use in indirect

addressing. When the ARP is loaded, the previous ARP value is copied to the ARB register, ex-

cept during an LST (load status register) instruction. The ARP may be modified by memory-refer-

ence instructions using indirect addressing, and by the MAR (modify auxiliary register) and LST

instructions. When the ARB is loaded by an LST instruction, the same value is also copied to the

ARP. For more details on the use of ARP in indirect addressing, see Section 6.3,

Indirect Addres-

sing Mode, on page 6-9.

Carry bit

. This bit is set to 1 if the result of an addition generates a carry, or cleared to 0 if the result

of a subtraction generates a borrow. Otherwise, it is cleared after an addition or set after a subtrac-

tion, except if the instruction is ADD or SUB with a 16-bit shift. In these cases, ADD can only set

and SUB only clear the carry bit, but cannot affect it otherwise. The single-bit shift and rotate

instructions also affect this bit, as well as the SETC, CLRC, and LST instructions. The conditional

branch, call, and return instructions can execute, based on the status of C. C is set to 1 on reset.

CNF

On-chip DARAM configuration bit

. This bit determines whether reconfigurable dual-access

RAM blocks are mapped to data space or to program space. The CNF bit may be modified by the

SETC CNF, CLRC CNF, and LST instructions. Reset clears the CNF bit to 0. For more information

about CNF and the dual-access RAM blocks, see Chapter 3,

Memory and I/O Spaces.

CNF = 0

Reconfigurable dual-access RAM blocks are mapped to data space.

CNF = 1

Reconfigurable dual-access RAM blocks are mapped to program space.

Data page pointer. When an instruction uses direct addressing, the 9-bit DP field is concatenated

with the seven LSBs of the instruction word to form a full 16-bit data-memory address. For more

details, see Section 6.2,

Direct Addressing Mode, on page 6-4. The LST and LDP (load DP)

instructions can modify the DP field.

INTM

Interrupt mode bit

. This bit enables or disables all maskable interrupts. INTM is set and cleared

by the SETC INTM and CLRC INTM instructions, respectively. INTM has no effect on the non-

maskable interrupts RS and NMI or on interrupts initiated by software. INTM is unaffected by the

LST (load status register) instruction. INTM is set to 1 when an interrupt trap is taken (except in

the case of the TRAP instruction) and at reset.

INTM = 0

All unmasked interrupts are enabled.

INTM = 1

All maskable interrupts are disabled.

Overflow flag bit. This bit holds a latched value that indicates whether overflow has occurred in

the CALU. OV is set to 1 when an overflow occurs in the CALU. Once an overflow occurs, the OV

bit remains set until it is cleared by a reset, a conditional branch on overflow (OV) or no overflow

(NOV), or an LST instruction.

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