TMS320F datasheet(27/389 Pages) TI

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’C24x CPU Internal Bus Structure

2-4

2.2

’C24x CPU Internal Bus Structure

The ’C24x DSP, a member of the TMS320 family of DSPs, includes a ’C2xx

DSP core designed using the ’2xLP ASIC core. The ’C2xx DSP core has an

internal data and program bus structure that is divided into six 16-bit buses

(see Figure 2–2). The six buses are:

- PAB. The program address bus provides addresses for both reads from

and writes to program memory.

- DRAB. The data-read address bus provides addresses for reads from

data memory.

- DWAB. The data-write address bus provides addresses for writes to data

memory.

- PRDB. The program read bus carries instruction code and immediate op-

erands, as well as table information, from program memory to the CPU.

- DRDB. The data-read bus carries data from data memory to the central

arithmetic logic unit (CALU) and the auxiliary register arithmetic unit

(ARAU).

- DWEB. The data-write bus carries data to both program memory and data

memory.

Having separate address buses for data reads (DRAB) and data writes

(DWAB) allows the CPU to read and write in the same machine cycle.

Figure 2–2. ’C24x Address and Data Bus Structure

DARAM

Flash/

ROM

B1, B2

DARAM

Memory-

mapped

registers

PAB

DRAB

DWAB

PRDB

DRDB

DWEB

Central processing unit (CPU)

External

address bus

External

data bus

System module

External bus

interface

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