MPC8313E datasheet(18/88 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

DDR and DDR2 SDRAM

6.2

DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR and DDR2 SDRAM Input AC Timing Specifications

Table 16 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ)=1.8 V.

Table 17 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V.

Table 18 provides the input AC timing specifications for the DDR2 SDRAM interface.

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GVDD of 1.8 ±5%

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.25

AC input high voltage

VIH

MVREF + 0.25

—

Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions with GVDD of 2.5 ±5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.31

AC input high voltage

VIH

MVREF + 0.31

—

Table 18. DDR and DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions. with GVDD of 2.5 ±5%

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for

MDQS—MDQ//MDM

tCISKEW

1, 2

333 MHz

–750

750

266 MHz

–750

750

200 MHz

–1250

1250

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any

corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This

can be determined by the following equation: tDISKEW = +/–(T/4 – abs(tCISKEW)) where T is the clock period

and abs(tCISKEW) is the absolute value of tCISKEW.

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