XRT86VL34 datasheet(31/156 Pages) EXAR

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XRT86VL34

REV. V1.2.0

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 11: RECEIVE SIGNALING & DATA LINK SELECT REGISTER (RSDLSR)

HEX ADDRESS: 0Xn10C

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

Reserved

5-4

RxDLBW[1:0]

R/W

Receive Data Link Bandwidth[1:0]:

These two bits select the bandwidth for data link message reception.

Data Link messages can be received at a 4kHz rate or at a 2kHz rate

on odd or even framing bits depending on the configuration of these

bits. The table below specifies the different configurations.

NOTE: This bit only applies to T1 ESF framing format. For SLC96 and

N framing formats, FDL is a 4kHz data link channel. For T1DM,

FDL is a 8kHz data link channel.

3-2

RxDE[1:0]

R/W

Receive D/E Time-Slot Destination Select[1:0]:

These bits permit the user to specify the “destination” circuitry that will

receive and process the D/E-Time-slot within the incoming T1 data-

stream.

RXDLBW[1:0]

RECEIVE DATA LINK BANDWIDTH SELECTED

Received Data link bits are extracted in every

frame. Facility Data Link Bits (FDL) is a 4kHz data

link channel.

Received Data link bits are extracted in every

other frame. Facility Data Link Bits (FDL) is a 2kHz

data link channel carried by odd framing bits

(Frames 1,5,9.....)

Received Data link bits are extracted in every

other frame. Facility Data Link Bits (FDL) is a 2kHz

data link channel carried by even framing bits

(Frames 3,7,11.....)

Reserved

RXDE[1:0]

DESTINATION CIRCUITRY FOR

RECEIVE D/E TIME-SLOT

RxSER_n output pin - The D/E time slots are out-

put to the receive serial data output pin (RxSER_n)

pin.

Receive LAPD Controller Block - The D/E time

slots are output to Receive LAPD Controller Block.

Reserved

RxFRTD_n output pin- The D/E time slots are

output to the receive fractional output pin.

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