XRT86VL34 datasheet(43/156 Pages) EXAR

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XRT86VL34

REV. V1.2.0

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 23: INTERRUPT CONTROL REGISTER (ICR)

HEX ADDRESS: 0Xn11A

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

7-3

Reserved

INT_WC_RUR

R/W

Interrupt Write-to-Clear or Reset-upon-Read Select

This bit configures all Interrupt Status bits to be either Reset Upon

Read or Write-to-Clear

0= Configures all Interrupt Status bits to be Reset-Upon-Read

(RUR).

1= Configures all Interrupt Status bits to be Write-to-Clear (WC).

ENBCLR

R/W

Interrupt Enable Auto Clear

This bit configures all interrupt enable bits to clear or not clear after

reading the interrupt status bit.

0= Configures all Interrupt Enable bits to not cleared after reading

the interrupt status bit. The corresponding Interrupt Enable bit will

stay ‘high’ after reading the interrupt status bit.

1= Configures all interrupt Enable bits to clear after reading the

interrupt status bit. The corresponding interrupt enable bit will be set

to ‘low’ after reading the interrupt status bit.

INTRUP_ENB

R/W

Interrupt Enable for Framer_n

This bit enables or disables the entire T1 Framer Block for Interrupt

Generation.

0 = Disables the T1 framer block for Interrupt Generation

1 = Enables the T1 framer block for Interrupt Generation

TABLE 24: LAPD SELECT REGISTER (LAPDSR)

HEX ADDRESS: 0Xn11B

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

[7:2] Reserved

Reserved

[1:0] HDLC Controller

Select[1:0]

R/W

HDLC Controller Select[1:0]:

These bits permit the user to select any of the three (3) HDLC Con-

trollers that he/she will use within this particular channel, as

depicted below.

00 & 11 - Selects HDLC Controller # 1

01 - Selects HDLC Controller # 2

10 - Selects HDLC Controller # 3

XRT86VL34 Datasheet(PDF) 43 Page - Exar Corporation

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