SAF7113 datasheet(6/80 Pages) PHILIPS

6 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

PINNING

SYMBOL

I/O/P

DESCRIPTION

AI22

analog input 22

VSSA1

ground for analog supply voltage channel 1

VDDA1

positive supply voltage for analog channel 1 (+3.3 V)

AI11

analog input 11

AI1D

differential analog input for AI11 and AI12; has to be connected to ground via a

capacitor; see application diagram of Fig.31

AGND

analog signal ground connection

AI12

analog input 12

TRST

test reset input (active LOW), for boundary scan test; notes 1, 2 and 3

AOUT

analog test output; for testing the analog input channels, 75

Ω termination possible

VDDA0

positive supply voltage (+3.3 V) for internal Clock Generation Circuit (CGC)

VSSA0

ground for internal clock generation circuit

VPO7 to

VPO4

12 to 15

digital VPO-bus output signal; higher bits of the 8-bit output bus. The output data

types of the VPO-bus are controlled via I2C-bus registers LCR2 to LCR24;

see Table 4. If I2C-bus bit VIPB = 1, the higher bits of the digitized input signal are

connected to these outputs, conﬁgured by the I2C-bus control signals

MODE3 to MODE0

VSSDE1

ground 1 or digital supply voltage input E (external pad supply)

LLC

line-locked system clock output (27 MHz)

VDDDE1

digital supply voltage E1 (external pad supply 1; +3.3 V)

VPO3 to

VPO0

19 to 22

digital VPO-bus output signal; lower bits of the 8-bit output bus. The output data types

of the VPO-bus are controlled via I2C-bus registers LCR2 to LCR24; see Table 4.

If I2C-bus bit VIPB = 1, the lower bits of the digitized input signal are connected to

these outputs, conﬁgured by the I2C-bus control signals MODE3 to MODE0

SDA

I/O

serial data input/output (I2C-bus) 5 V-compatible

SCL

serial clock input (I2C-bus) 5 V-compatible

RTCO

(I/)O

real-time control output: contains information about actual system clock frequency,

ﬁeld rate, odd/even sequence, decoder status, subcarrier frequency and phase and

PAL sequence (see external document

“RTC Functional Description”, available on

request); the RTCO pin is enabled via I2C-bus bit OERT; this pin is also used as an

input pin for test purposes and has an internal pull-down resistor; do not

connect any pull-up resistor to this pin

RTS0

(I/)O

real-time signal output 0: multi functional output, controlled by I2C-bus bits

RTSE03 to RTSE00; see Table 49. RTS0 is strapped during power-on or CE driven

reset, deﬁnes which I2C-bus slave address is used; 0 = 48H for write, 49H for read,

external pull-down resistor of 3.3 k

Ω is needed; 1 = 4AH for write, 4BH for read,

default slave address (default, internal pull-up)

RTS1

I/O

real-time signal I/O terminal 1: multi functional output, controlled by I2C-bus bit

RTSE13 to RTSE10; see Table 50

VSSDI

ground for internal digital core supply

VDDDI

internal core supply (+3.3 V)

VSSDA

digital ground for internal crystal oscillator

XTAL

second terminal of crystal oscillator; not connected if external clock signal is used

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