SAF7113 datasheet(69/80 Pages) PHILIPS

69 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

15.2.23 SUBADDRESS 17H

Table 54 VGATE MSBs

15.2.24 SUBADDRESS 1FH (READ ONLY REGISTER)

Table 55 Status byte video decoder SA 1F

FUNCTION

LOGIC LEVEL

CONTROL BIT

VSTA8, see SA 15

MSB VGATE start

see Table 52

VSTO8, see SA 16

MSB VGATE stop

see Table 53

I2C-BUS

CONTROL BIT

FUNCTION

DATA BIT

RDCAP

ready for capture (all internal loops locked); active HIGH (OLDSB = 0)

CODE

colour signal in accordance with selected standard has been detected; active HIGH

(OLDSB = 1)

COPRO

copy protected source detected according to macrovision version up to 7.01

(OLDSB = 0)

SLTCA

slow time constant active in WIPA mode; active HIGH (OLDSB = 1)

WIPA

white peak loop is activated; active HIGH

GLIMB

gain value for active luminance channel is limited [min (bottom)]; active HIGH

GLIMT

gain value for active luminance channel is limited [max (top)]; active HIGH

FIDT

identiﬁcation bit for detected ﬁeld frequency; LOW = 50 Hz, HIGH = 60 Hz

HLVLN

status bit for horizontal/vertical loop: LOW = locked, HIGH = unlocked (OLDSB = 0)

HLCK

status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked

(OLDSB = 1)

INTL

status bit for interlace detection; LOW = non-interlaced, HIGH = interlaced

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