SMC032BFY6 datasheet(24/91 Pages) STMICROELECTRONICS

24 / 91 page

Command Interface

SMCxxxBF

24/91

Command Interface

There are two types of bus cycles and timing sequences that occur in the PCMCIA type

interface, direct mapped I/O transfer and memory access. Two types of bus cycles are also

available in True IDE interface type: PIO transfer and Multi-Word DMA transfer.

Table 16, Table 17, Table 18, Table 19, Table 20, Table 21 and Table 22 show the read and

write timing parameters. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure and

Figure 8 show the read and write timing diagrams.

In order to set the card mode, the -OE (-ATASEL) signal must be set and kept stable before

applying VCC until the reset phase is completed. To place the card in Memory mode or I/O

mode, -OE(-ATASEL) must be driven High, while it must be driven Low to place the card in

True IDE mode.

5.1

Attribute Memory Read and Write

Figure 2.

Attribute Memory Read waveforms

DOUT signifies data provided by the CompactFlash Memory Card to the system. The -CE signal or both the -OE signal and

the -WE signal must be de-asserted between consecutive cycle operations.

AI10080

tc(R)

ta(A)

tv(A)

ta(CE)

ten(OE)

VALID

Address Inputs

D0 to D15 (DOUT)

VALID

–REG

–CE2/–CE1

–OE

tsu(A)

ten(CE)

tdis(OE)

tdis(CE)

ta(OE)

Table 16.

Attribute Memory Read timing

Speed Version

300ns

Symbol

IEEE Symbol

Parameter

Min

Max

Unit

tc(R)

tAVAV

Read Cycle Time

300

ta(A)

tAVQV

Address Access Time

300

ta(CE)

tELQV

CE Access Time

300

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