SMC032BFY6 datasheet(44/91 Pages) STMICROELECTRONICS

44 / 91 page

Software interface

SMCxxxBF

44/91

Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd

addresses between 400h and 7FFh access register 9. This 1 KByte memory window to the

data register is provided so that hosts can perform memory-to-memory block moves to the

data register when the register lies in memory space. Some hosts, such as the X86

processors, must increment both the source and destination addresses when executing the

memory-to-memory block move instruction. Some PCMCIA socket adapters also have an

embedded auto incrementing address logic.

A Word access to address at offset 8 will provide even data on the least significant Byte of

the data bus, along with odd data at offset 9 on the most significant Byte of the data bus.

Table 37.

Memory Mapped Decoding

–

REG A10

A9 to

A3 A2 A1 A0 Offset

–

OE=0

–

WE=0

0000

Even Data Register

0001

Error Register

Feature Register

0010

Sector Count

Sector Count Register

0011

Sector Number

Sector Number Register

0100

Cylinder Low Register

0101

Cylinder High

Cylinder High Register

0110

Select Card/Head

0111

Status Register

Command Register

1000

Dup. Even Data

Dup. Even Data Register

1001

Dup. Odd Data

Dup. Odd Data Register

1101

Dup. Error Register

Dup. Feature Register

1110

Alternate Status

Device Control Register

1111

Drive Address

Reserved

Even Data Register

Odd Data Register

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