SMC032BFY6 datasheet(48/91 Pages) STMICROELECTRONICS

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CF-ATA registers

SMCxxxBF

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CF-ATA registers

The following section describes the hardware registers used by the host software to issue

commands to the Card. These registers are collectively referred to as the ‘task file’.

In accordance with the PCMCIA specification, each register that is located at an odd offset

address can be accessed in the PC Card Memory or PC Card I/O modes. The register can

be addressed in two ways:

●

Using the normal register address.

●

Using the corresponding even address (normal address -1) when -CE1 is High and -

CE2 Low, unless -IOIS16 is High (not asserted by the card) and an I/O cycle is in

progress. Register data are input or output on data bus lines D15-D8.

In True IDE mode, the size of the transfer is based solely on the register being addressed.

All registers are 8-bit only except for the Data Register, which is normally 16 bits. However,

they can be configured to be accessed in 8-bit mode for non-DMA operations, by using a

Set Features command (see Section 10.17).

9.1

Data Register

The Data register is located at address 1F0h [170h], offset 0h, 8h, and 9h.

The Data Register is a 16 bit register used to transfer data blocks between the Card data

buffer and the Host. This register overlaps the Error Register. Table 41 and Table 42

describes the combinations of Data register access and explains the overlapped Data and

Error/Feature Registers. Because of the overlapped registers, access to the 1F1h, 171h or

offset 1 are not defined for Word (–CE2 and –CE1 set to ‘0’) operations, and are treated as

accesses to the Word Data Register. The duplicated registers at offsets 8, 9 and Dh have no

restrictions on the operations that can be performed.

Table 41.

Data Register Access (Memory and I/O mode)

Data Register

–CE2

–CE1

-REG(1)

Offset

Data Bus

Word Data Register

0h, 8h, 9h

D15 to D0

Even Data Register

0h, 8h

D7 to D0

Odd Data Register

D7 to D0

Odd Data Register

8h, 9h

D15 to D8

Error/Feature Register

1h, Dh

D7 to D0

Error/Feature Register

D15 to D8

Error/Feature Register

D15 to D8

-REG signal is mode dependent. It must be Low when the Card operates in I/O Mode and High when it operates in Memory

Mode.

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