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M30302FAPFP Datasheet(PDF) 34 Page - Renesas Technology Corp |
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M30302FAPFP Datasheet(HTML) 34 Page - Renesas Technology Corp |
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34 / 57 page ![]() M16C/30P Group 5. Electrical Characteristics Rev.1.22 Mar 30, 2007 Page 34 of 53 REJ03B0088-0122 VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. Calculated according to the BCLK frequency as follows: f(BCLK) is 12.5MHz or less. 2. Calculated according to the BCLK frequency as follows: 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR X ln (1−VOL / VCC1) by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1k Ω, hold time of output ”L” level is t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1) = 6.7ns. Figure 5.2 Ports P0 to P10 Measurement Circuit Table 5.25 Memory Expansion and Microprocessor Modes (for setting with no wait) Symbol Parameter Standard Unit Min. Max. td(BCLK-AD) Address Output Delay Time See Figure 5.2 25 ns th(BCLK-AD) Address Output Hold Time (in relation to BCLK) −3ns th(RD-AD) Address Output Hold Time (in relation to RD) 0 ns th(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 2) ns td(BCLK-CS) Chip Select Output Delay Time 25 ns th(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) −3ns td(BCLK-ALE) ALE Signal Output Delay Time 15 ns th(BCLK-ALE) ALE Signal Output Hold Time −4ns td(BCLK-RD) RD Signal Output Delay Time 25 ns th(BCLK-RD) RD Signal Output Hold Time 0 ns td(BCLK-WR) WR Signal Output Delay Time 25 ns th(BCLK-WR) WR Signal Output Hold Time 0 ns td(BCLK-DB) Data Output Delay Time (in relation to BCLK) 40 ns th(BCLK-DB) Data Output Hold Time (in relation to BCLK) (3) 4ns td(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 1) ns th(WR-DB) Data Output Hold Time (in relation to WR) (3) (NOTE 2) ns td(BCLK-HLDA) HLDA Output Delay Time 40 ns 0.5x10 9 fBCLK () ------------------------40 ns [] – 0.5x10 9 fBCLK () ------------------------10 ns [] – DBi R C P6 P7 P8 P10 P9 P0 P1 P2 P3 P4 P5 30pF |
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