M30302FAPFP datasheet(39/57 Pages) RENESAS

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M16C/30P Group

5. Electrical Characteristics

Rev.1.22

Mar 30, 2007

Page 39 of 53

REJ03B0088-0122

Figure 5.6

Timing Diagram (4)

BCLK

CSi

td(BCLK-CS)

25ns.max

ADi

25ns.max

ALE

25ns.max

-4ns.min

25ns.max

th(BCLK-RD)

0ns.min

th(BCLK-AD)

−3ns.min

th(BCLK-CS)

−3ns.min

Hi-Z

DBi

th(RD-DB)

0ns.min

th(RD-AD)

BHE

tcyc

Read timing

td(BCLK-AD)

td(BCLK-ALE)

th(BCLK-ALE)

tsu(DB-RD)

td(BCLK-RD)

40ns.min

tac1(RD-DB)

Memory Expansion Mode, Microprocessor Mode

(For setting with no wait)

Measuring conditions

· VCC1=VCC2=5V

· Input timing voltage : VIL=0.8V, VIH=2.0V

· Output timing voltage : VOL=0.4V, VOH=2.4V

WR, WRL,

WRH

25ns.max

th(BCLK-WR)

0ns.min

BCLK

CSi

td(BCLK-CS)

25ns.max

ADi

td(BCLK-AD)

25ns.max

ALE

25ns.max

td(BCLK-ALE)

th(BCLK-ALE)

-4ns.min

th(BCLK-AD)

−3ns.min

th(BCLK-CS)

−3ns.min

tcyc

th(WR-AD)

BHE

td(BCLK-DB)

40ns.max

4ns.min

th(BCLK-DB)

td(DB-WR)

(0.5

× tcyc-40)ns.min

th(WR-DB)

DBi

Write timing

td(BCLK-WR)

Hi-Z

(0.5

× tcyc-45)ns.max

tcyc=

f(BCLK)

(0.5

× tcyc-10)ns.min

(0.5

× tcyc-10)ns.min

VCC1=VCC2=5V

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