PCA9641PW datasheet(22/55 Pages) NXP

22 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

22 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

8.8 Operating cycle of the downstream bus

8.8.1 Request the downstream bus

When a master seeks control of the bus by requesting its I2C-bus channel to the PCA9641

registers, it must write to the Control register (CONTR, 01h) and Reserve Time register

(RT, 03h) optional. LOCK_REQ bit and RT[7:0] allow the master to take control of the bus

in a period of RES_TIME without interrupting.

While master 0 is working on the downstream bus, master 1 can request the downstream

bus by writing to LOCK_REQ bit in CONTR register and RT register. When the

downstream bus is free and RES_TIME is expired, master 1 will have control of the

downstream bus.

If Reserve Time is set to 0, it will disable the timer counter. That means the master

requests the downstream bus forever or until it gives up the bus.

8.8.2 Acquire the downstream bus

After the master wrote to LOCK_REQ bit and RT register, it must poll LOCK_GRANT bit in

CONTR register or wait for interrupt signal (INTx pin) if LOCK_GRANT_MSK bit is set in

INT_MSK register for the ownership of the downstream bus.

When LOCK_GRANT bit is one, this master has full control of the downstream bus.

To start communication with downstream slave devices, master must connect to

downstream bus by setting BUS_CONNECT = 1.

8.8.3 Give up the downstream bus

The RES_TIME starts countdown after LOCK_GRANT becomes one. When the

RES_TIME becomes zero and the I2C-bus is free (SCL_SLAVE and SDA_SLAVE are

HIGH) after STOP condition, PCA9641 will clear the LOCK_GRANT bit.

If a master requests the downstream bus with RES_TIME = 0, it must write zero to

LOCK_REQ bit to give up its control.

PCA9641PW Datasheet(PDF) 22 Page - NXP Semiconductors