PCA9641PW datasheet(27/55 Pages) NXP

27 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

27 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

12.4 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 14. System configuration

aaa-012277

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SDA

SCL

2-CHANNEL

I2C-BUS

MASTER ARBITER

PCA9641

SLAVE

RECEIVER

SLAVE

RECEIVER

MASTER 0

TRANSMITTER/

RECEIVER

MASTER 1

TRANSMITTER/

RECEIVER

SDA 0

SCL 0

SDA 1

SCL 1

Fig 15. Acknowledgement on the I2C-bus

002aaa987

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

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