PCA9641PW datasheet(10/55 Pages) NXP

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PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

10 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

7.3 Command Code

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9641, which will be stored in the Command Code register.

The 3 LSBs are used as a pointer to determine which register will be accessed. If the

auto-increment flag is set (AI = 1), the three least significant bits of the Command Code

are automatically incremented after a byte has been read or written. This allows the user

to program the registers sequentially or to read them sequentially.

• During a read operation, the contents of these bits will roll over to 000b after the last

allowed register is accessed (111b).

• During a write operation, the PCA9641 will acknowledge bytes sent to the CONTR,

STATUS, RT, INT_STATUS, INT_MSK, MB_LO and MB_HI registers, but will not

acknowledge bytes sent to the ID register since it is a read-only register. The 3 LSBs

of the Command Code do not roll over to 000b but stay at 111b.

Only the 3 least significant bits are affected by the AI flag.

Unused bits must be programmed with zeros. Any command code (write operation)

different from ‘AI000 0000’, ‘AI000 0001’, ‘AI000 0010’, ‘AI000 0011’, ‘AI000 0100’,

‘AI000 0101’, ‘AI000 0110’ and ‘AI000 111’ will not be acknowledged. At power-up, this

Each system master controls its own set of registers, however they can also read specific

bits from the other system master.

Fig 5.

Command Code

Table 6.

Command Code register

Type

R only

8-bit device ID

CONTR

R/W

control register

STATUS

R/W

status register

R/W

reserve time

INT_STATUS

R/W

interrupt status register

INT_MSK

R/W

interrupt mask register

MB_LO

R/W

low 8 bits of the mail box

MB_HI

R/W

high 8 bits of the mail box

aaa-008521

0000

number

auto-increment

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