PCA9641PW datasheet(25/55 Pages) NXP

25 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

25 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

11. Request grant examples

In the waveform shown in Figure 11, Master 0 initiated a START first. Master 1 was at a

higher clock speed and wrote the request bit first, so Master 1 won the arbitration.

The effects of the arbitration do not take effect until the winning master issues a STOP

condition. If the winning master were to continue to write to the next register using

auto-incrementing addresses, it would delay the grant until the STOP. The master has

‘won’ the arbitration, though.

Two masters request the bus at the same time (close enough that the logic cannot tell the

difference). See Figure 8 for the waveform. In this case the PRIORITY bits are used to

determine the winner. The truth table, Table 9, is for winner selection.

12. Characteristics of the I2C-bus

The information in this section pertains to both M0 and M1 I2C-bus interfaces.

The I2C-bus interface is used to access the device programmable registers. This interface

runs as Fast-mode Plus (Fm+) speeds with a general call software reset. The I2C core is

composed of the I2C State Machine, shift register, and the start/stop detection logic.

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

Fig 11. Request grant example

aaa-008554

ACK

M1 SDA

M1 SCL

M0 SDA

M0 SCL

grant

winner

Master 1

Master 0

none

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