PCA9641PW datasheet(38/55 Pages) NXP

38 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

38 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

Table 17 specifies the performance of the power-on reset feature for PCA9641 for both

types of power-on reset.

[1]

Glitch width and

V

DD voltage that will not cause a functional disruption.

Glitches in the power supply can also affect the power-on reset performance of this

device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each

other. The bypass capacitance, source impedance, and device impedance are factors that

affect power-on reset performance. Figure 29 and Table 17 provide more information on

how to measure these specifications.

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition

is released and all the registers and the I2C-bus/SMBus state machine are initialized to

their default states. The value of VPOR differs based on the VDD being lowered to or from

0V. Figure 30 and Table 17 provide more details on this specification.

Table 17.

Recommended supply sequencing and ramp rates

Tamb =25 C (unless otherwise noted). Not tested; specified by design.

Symbol

Parameter

Condition

Min

Typ

Max

Unit

(dV/dt)f

fall rate of change of voltage

Figure 27

0.1

2000

(dV/dt)r

rise rate of change of voltage

Figure 27

0.1

2000

td(rst)

reset delay time

Figure 27; re-ramp time when

VDD drops to VSS

s

Figure 28; re-ramp time when

VDD drops to VPOR(min)  50 mV

s

V

DD(gl)

glitch supply voltage difference

Figure 29

[1] --1

tw(gl)VDD

supply voltage glitch pulse width

Figure 29

[1] --10

s

VPOR(trip)

power-on reset trip voltage

falling VDD

0.7

--V

rising VDD

--1.8

tREC;STA

recovery time to START condition

refer to Figure 33

155

s

Fig 29. Glitch width and glitch height

002aah331

VDD

time

tw(gl)VDD

∆VDD(gl)

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