PCA9641PW datasheet(37/55 Pages) NXP

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PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

37 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

16.5 Bus initialization/recovery to initialize slaves without hardware reset

If the I2C-bus is hung, I2C-bus devices without a hardware reset pin (for example, Slave 1

and Slave 2 in Figure 26) can be isolated from the master by the PCA9641. The PCA9641

disconnects the hung bus if IDLE_TIMER_DIS was set or over 500 ms, restoring the

master's control of the rest of the bus (for example, Slave 0). The bus master can then

command the PCA9641 to send nine clock pulses/STOP condition to reset the

downstream I2C-bus devices before they are reconnected to the master or leave the

downstream devices isolated.

16.6 Power-on reset requirements

In the event of a glitch or data corruption, PCA9641 can be reset to its default conditions

by using the power-on reset feature. Power-on reset requires that the device go through a

power cycle to be completely reset. This reset also happens when the device is

powered on for the first time in an application.

The two types of power-on reset are shown in Figure 27 and Figure 28.

Fig 26. Bus initialization/recovery application

002aag824

PCA9641

SLAVE 1

SDA

SCL

SLAVE 2

slave I2C-bus

MASTER

SLAVE 0

RESET

SDA/SCL

Fig 27. VDD is lowered below 0.7 V or 0 V and then ramped up to VDD

Fig 28. VDD is lowered below the POR threshold, then ramped back up to VDD

aaa-013905

VDD

time

ramp-up

ramp-down

(dV/dt)r

(dV/dt)f

re-ramp-up

(dV/dt)r

time to re-ramp

when VDD drops

below 0.7 V or to VSS

td(rst)

002aah330

VDD

time

ramp-down

(dV/dt)f

ramp-up

(dV/dt)r

time to re-ramp

when VDD drops

to VPOR(min) − 50 mV

td(rst)

VI drops below POR levels

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