PM5366-PI datasheet(36/267 Pages) PMC

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

In the ingress direction, each of the 63 2.048 Mbit/s links is either demultiplexed

from a DS3 according to ITU-T Rec. G.747 or extracted from SONET/SDH VT2

or TU-12 mapped bus.

The E1 performance monitors support detection of various alarm conditions such

as loss of frame, loss of signaling multiframe and loss of CRC multiframe. The

E1 framers also support reception of remote alarm signal, remote multiframe

alarm signal, alarm indication signal, and time slot 16 alarm indication signal.

E1 performance monitoring with accumulation of CRC-4 errors, far end block

errors and framing bit errors is provided. The TEMAP-84 provides a receive

HDLC controller for the detection and termination of messages on the national

use bits.

The TEMAP-84 can generate a low jitter transmit clock from a variety of clock

references, and also provides jitter attenuation in the receive path. Three jitter

attenuated recovered T1/E1 clocks can be routed outside the TEMAP-84 for

network timing applications.

A Scaleable Bandwidth Interconnect (SBI) high density byte serial system

interface provides higher levels of integration and dense interconnect. The SBI

bus interconnects up to 84 T1s or 63 E1 both synchronously or asynchronously.

The SBI allows transmit timing to be mastered by either the TEMAP-84 or link

layer device connected to the SBI bus. In addition to unframed T1s and E1s, the

TEMAP-84 can transport framed or unframed DS3 or E3 links over the SBI bus.

When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TEMAP-

84 accepts and outputs either digital B3ZS-encoded bipolar or unipolar signals

compatible with M23 and C-bit parity applications.

In the DS3 receive direction, the TEMAP-84 frames to DS3 signals with a

maximum average reframe time of 1.5 ms in the presence of 10-3 bit error rate

and detects line code violations, loss of signal, framing bit errors, parity errors, C-

bit parity errors, far end block errors, AIS, far end receive failure and idle code.

The DS3 framer is an off-line framer, indicating both out of frame (OOF) and

change of frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.)

are still indicated while the framer is OOF, based on the previous frame

alignment. When in C-bit parity mode, the Path Maintenance Data Link and the

Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are

provided for Path Maintenance Data Link support. In addition, valid bit-oriented

codes in the FEAC channels are detected and are available through the

microprocessor port.

DS3 error event accumulation is also provided by the TEMAP-84. Framing bit

errors, line code violations, excessive zeros occurrences, parity errors, C-bit

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