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PM5366-PI Datasheet(PDF) 58 Page - PMC-Sierra, Inc

Part # PM5366-PI
Description  HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
PDF  267 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 58 Page - PMC-Sierra, Inc

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PRELIMINARY
PM5366 TEMAP-84
DATASHEET
PMC-2010672
ISSUE 1
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
46
Pin Name
Type
Pin
No.
Function
CLK52M
Input
AB10 52 MHz Clock Reference (CLK52M). The 52Mhz
clock reference is used to generate a gapped DS3
clock when demapping a DS3 from the SONET stream
and also to generate a gapped DS3/E3 clock when
receiving a DS3/E3 from the SBI bus interface. This
clock has two nominal values.The first is a nominal
51.84 MHz 50% duty cycle clock. The second is a
nominal 44.928 MHz 50% duty cycle clock. The
expected frequency is determined by the
FASTCLKFREQ bit of the SONET/SDH Master DS3
Clock Generation Control register. If E3 data rates are
being supported, CLK52M must be 51.84MHz.
Scaleable Bandwidth Interconnect Interface
CTCLK
Input
F19 Common Transmit Clock (CTCLK). This input signal
is used as a reference transmit tributary clock which
can be used in egress Clock Master modes. CTCLK
must be multiple of 8 kHz. The transmit clock is
derived by the jitter attenuator PLL using CTCLK as a
reference.
The TEMAP may be configured to ignore the CTCLK
input and lock to the data or one of the recovered
Ingress clocks instead, RECVCLK1, RECVCLK2 and
RECVCLK3. The receive tributary clock is
automatically substituted for CTCLK if line loopback or
looptiming is enabled.
SREFCLK
Input
C10 System Reference Clock (SREFCLK). This system
reference clock is a nominal 19.44 MHz +/-50ppm or
77.76 MHz +/-50ppm 50% duty cycle clock. This clock
is common to both the add and drop sides of the SBI
bus.
SREFCLK must be active for all applications, except
DS3/E3 framer only mode when the system interface is
serial clock and data. When the SYSOPT register bits
are binary 01 (H-MVIP interface), SREFCLK is
required to be 19.44 MHz.
When passing transparent virtual tributaries between
the telecom bus and the SBI bus, SREFCLK must be
the same as LREFCLK.



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