PM7344 datasheet(99/293 Pages) PMC

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PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Registers 007H, 107H, 207H and 307H: Transmit Timing Options

Bit

Type

Function

Default

Bit 7

R/W

FIFOBYP

Bit 6

R/W

XCLKSEL

Bit 5

Unused

Bit 4

R/W

OCLKSEL

Bit 3

R/W

TREF[1]

Bit 2

R/W

TREF[0]

Bit 1

Unused

Bit 0

Unused

When the T1 or E1 format is selected, these registers allow software to configure

the options of the transmit timing section.

FIFOBYP:

The FIFOBYP bit enables the transmit input signals to DJAT to be bypassed

around the FIFO to the outputs. When jitter attenuation is not being used,

the DJAT FIFO can be bypassed to reduce the delay through the transmitter

section by typically 24 bits. When FIFOBYP is set to logic 1, the inputs to

DJAT are routed around the FIFO to the outputs. When FIFOBYP is set to

logic 0, the transmit data passes through the DJAT FIFO. When the T1 or E1

format is not enabled, the FIFO is automatically bypassed.

XCLKSEL:

The XCLKSEL bit selects the source of the high-speed clock used in the

CDRC and FRMR blocks. When XCLKSEL is set to logic 1, the XCLK input

signal is used as the high-speed clock to these blocks. XCLK must be driven

with clock that is 8 times the nominal bit rate (12.352 MHz for T1 or 16.384

MHz for E1). When XCLKSEL is set to logic 0, the high-speed clock is driven

by XCLK divided by 3. XCLK must be driven with a clock that is 24 times the

nominal bit rate (37.056MHz for T1 or 49.152 MHz for E1). XCLK must be

set to logic 0 when jitter attenuation is enabled.

OCLKSEL:

The OCLKSEL bit selects the source of the Digital Jitter Attenuator FIFO

output clock signal. When OCLKSEL is set to logic 1, the DJAT FIFO output

clock is driven with the transmit reference clock as selected by the TREF[1:0]

inputs. In this mode the jitter attenuation is disabled and the input clock must

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