CYRF69103
Document #: 001-07611 Rev *B
Page 4 of 73
Pinout Diagram
Figure 1. Pinout
Functional Block Overview
All the blocks that make up the PRoC LP are presented here.
2.4-GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
Frequency Synthesizer
Before transmission or reception may commence, it is
necessary for the frequency synthesizer to settle. The settling
time varies depending on channel; 25 fast channels are
provided with a maximum settling time of 100
µs.
The “fast channels” (<100-
µs settling time) are every 3rd
frequency, starting at 2400 MHz up to and including 2472 MHz
(i.e., 0,3,6,9…….69 & 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, as well as EOP detection and length
field.
41
E-pad
GND
Pinout
Pin
Name
Function/Description
40-pin Lead-Free QFN 6x6 mm LY40
RFBIAS
VBAT
XTAL
P2.1
VCC
VBAT
P0.4
VCC
P0.1
P0.3
VDD_Micro
P1.3 / SS
P1.4 / SCK
IRQ / GPIO
P1.5 / MOSI
MISO / GPIO
XOUT / GPIO
P1.2 / VREG
P1.1
P1.0
* E-PAD Bottom Side
21
22
23
24
25
26
27
28
29
30
10
9
8
7
6
5
4
3
2
1
CYRF69103
WirelessUSB LP
Corner
tabs
Table 1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
7
+4
6
0
5
–5
4
–10
3
–15
2
–20
1
–25
0
–30
Table 1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
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