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CYRF69103
Document #: 001-07611 Rev *B
Page 21 of 73
Table 33.OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved
No Buzz
Sleep Timer [1:0]
CPU Speed [2:0]
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bits 7:6
Reserved
Bit 5
No Buzz
During sleep (the Sleep bit is set in the CPU_SCR Register—
Table 37), the LVD and POR detection circuit is turned on period-
ically to detect any POR and LVD events on the VCC pin (the Sleep Duty Cycle bits in the ECO_TR are used to control the duty
cycle—
Table 41). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the LVD and POR detec-
tion circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR event during sleep at the
expense of a slightly higher than average sleep current. Obtaining the absolute lowest power usage in sleep mode requires the
No Buzz bit be clear
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled
Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below
Bits 4:3
Sleep Timer [1:0]
Note Sleep intervals are approximate
Bits 2:0
CPU Speed [2:0]
The CYRF69103 ma y operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the
default CPU speed is 3 MHz.
Sleep Timer [1:0]
Sleep Timer Clock
Frequency (Nominal)
Sleep Period
(Nominal)
Watchdog Period
(Nominal)
00
512 Hz
1.95 ms
6 ms
01
64 Hz
15.6 ms
47 ms
10
8 Hz
125 ms
375 ms
11
1 Hz
1 sec
3 sec
CPU Speed [2:0]
CPU when Internal
Oscillator is selected
External Clock
000
3 MHz (Default)
Clock In/8
001
6 MHz
Clock In/4
010
12 MHz
Clock In/2
011
Reserved
Reserved
100
1.5 MHz
Clock In/16
101
750 KHz
Clock In/32
110
187 KHz
Clock In/128
111
Reserved
Reserved
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