CYRF69103
Document #: 001-07611 Rev *B
Page 3 of 73
Backward Compatibility
The CYRF69103 IC is fully interoperable with the main modes
of other Cypress radios CYWUSB6934 and CYRF69103. The
62.5-kbps
mode
is
supported
by
selecting
32-chip
DATA_CODE_ADR codes, DDR mode, and disabling the
SOP, length, and CRC16 fields. Similarly, the 15.675-kHz
mode is supported by selecting 64-chip DATA_CODE_ADR
codes and SDR mode.
In this way, a suitably configured CYRF69103 IC device may
transmit data to and/or receive data from a first generation
device.
Pinout
Pin
Name
Function/Description
1
P0.4
Individually configured GPIO
2
XTAL
12 MHz crystal
3, 7, 16
VCC
2.4V to 3.6V supply. Connected to pin 40 (0.047-
µF bypass)
4
P0.3
Individually configured GPIO
5
P0.1
Individually configured GPIO
6
Vbat1
Connect to 1.8V to 3.6V power supply, through 47-ohm series/1-
µF shunt C
8
P2.1
GPIO. Port 2 Bit 1
9
Vbat2
Connected to1.8V to 3.6V main power supply, through 0.047-
µF bypass C
10
RFbias
RF pin voltage reference
11
RFp
Differential RF to/from antenna
12
GND
GND
13
RFn
Differential RF to/from antenna
14, 17, 18, 20
NC
15
P2.0
GPIO
19
RESV
Reserved. Must connect to GND
21
P1.0
GPIO
22
P1.1
GPIO
23
VDD_micro
MCU supply connected to pin 40, max CPU 12 MHz
24
P1.2
GPIO
25
P1.3 / nSS
Slave Select
26
P1.4 / SCK
SPI Clock
27
IRQ
Radio Function Interrupt output, configure High, Low or as Radio GPIO
28
P1.5 / MOSI
MOSI pin from microcontroller function to radio function
29
MISO
3-wire SPI mode configured as Radio GPIO. In 4-wire SPI mode sends data to MCU function
30
XOUT
Buffered CLK, PACTL_n or Radio GPIO
31
PACTL
Control for external PA or Radio GPIO
32
P1.6
GPIO
33
VIO
1.8V to 3.6V to main power supply rail for Radio IO
34
RST
Radio Reset. Connected to pin 40 with 0.47
µF. Must have a RST=HIGH event the very first
time power is applied to the radio otherwise the state of the radio control registers is unknown
35
P1.7
GPIO
36
VDD1.8
Regulated logic bypass. Connected to 0.47
µF to GND
37
L/D
Inductor/Diode connection for Boost. When Internal PMU is not being used connect L/D to
GND.
38
P0.7
GPIO
39
Vbat0
Connected to1.8V to 3.6V main power supply, through 0.047-
µF bypass C
40
VREG
Boost regulator output voltage feedback
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
