PCA9665D datasheet(71/91 Pages) PHILIPS

71 / 91 page

PCA9665_2

Product data sheet

Rev. 02 — 7 December 2006

71 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I2C-bus controller

13. Dynamic characteristics

[1]

Parameters are valid over speciﬁed temperature and voltage range.

[2]

All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of

5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figure 38 and Figure 40.

[3]

Test conditions for outputs: CL = 50 pF; RL = 500 Ω, except open-drain outputs.

Test conditions for open-drain outputs: CL = 50 pF; RL =1kΩ pull-up to VDD.

[4]

Initialization time for the serial interface after ENSIO bit goes HIGH in a write operation to the control register.

[5]

Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.

[6]

Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA and SCL bus.

Table 49.

Dynamic characteristics (3.3 volt)[1][2][3]

VCC = 3.3 V ± 0.3 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed. (See Table 50 on page 72 for 2.5 V)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Initialization timing

tinit(po)

power-on initialization time

550

µs

Serial interface initialization timing

tinit(sintf)

serial interface initialization time[4]

from ENSIO bit HIGH

550

µs

RESET timing (see Figure 36)

tw(rst)

reset pulse width

trst

reset time

[5][6] 250

trec(rst)

reset recovery time

INT timing (see Figure 37)

tas(int)

interrupt assert time

500

tdas(int)

interrupt de-assert time

Bus timing (see Figure 38 and Figure 40)

tsu(A)

address setup time

to RD, WR LOW

th(A)

address hold time

from RD, WR LOW

tsu(CE_N)

CE setup time

to RD, WR LOW

th(CE_N)

CE hold time

from RD, WR LOW

tw(RDL)

RD LOW pulse width

tw(WRL)

WR LOW pulse width

td(DV)

data valid delay time

after RD and CE LOW

td(QZ)

data output ﬂoat delay time

after RD or CE HIGH

tsu(Q)

data output setup time

before WR or CE HIGH (write cycle)

th(Q)

data output hold time

after WR HIGH

tw(RDH)

RD HIGH pulse width

tw(WRH)

WR HIGH pulse width

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