PCA9665D datasheet(17/91 Pages) PHILIPS

17 / 91 page

PCA9665_2

Product data sheet

Rev. 02 — 7 December 2006

17 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I2C-bus controller

P — STOP condition

In Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13 and Figure 14,

circles are used to indicate when the serial interrupt ﬂag is set. A serial interrupt is not

generated when I2CSTA = F8h. This happens on a STOP condition or when an external

reset is generated (at power-up, when RESET pin is going LOW or during a software reset

on the parallel bus). The numbers in the circles show the status code held in the I2CSTA

serial transfer. These service routines are not critical since the serial transfer is

suspended until the serial interrupt ﬂag is cleared by software.

When a serial interrupt routine is entered, the status code in I2CSTA is used to branch to

the appropriate service routine. For each status code, the required software action and

details of the following serial transfer are given in Table 27, Table 28, Table 31, Table 32,

Table 35, Table 36, Table 40, and Table 41.

8.3 Byte mode

8.3.1 Master Transmitter Byte mode

In the Master Transmitter Byte mode, a number of data bytes are transmitted to a slave

receiver (see Figure 7). Before the Master Transmitter Byte mode can be entered,

I2CCON must be initialized as shown in Table 26.

ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665

will not acknowledge its own slave address in the event of another device becoming

master of the bus. (In other words, if AA is reset, PCA9665 cannot enter a slave mode.)

STA, STO, and SI must be reset. Once ENSIO has been set to 1, it takes about 550

µsfor

the oscillator to start up.

The Master Transmitter Byte mode may now be entered by setting the STA bit. The

I2C-bus state machine will ﬁrst test the I2C-bus and generate a START condition as soon

as the bus becomes free. When a START condition is transmitted, the serial interrupt ﬂag

(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register

(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service

routine that loads I2CDAT with the slave address and the data direction bit (SLA+W). A

write to I2CCON resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the

serial transfer to continue.

When the slave address with the direction bit have been transmitted, the Serial Interrupt

ﬂag (SI) is set again, the Interrupt line (INT) goes LOW again and I2CSTA is loaded with

the following possible codes:

• 18h if an acknowledgment bit (ACK) has been received

• 20h if an no acknowledgment bit (NACK) has been received

• 38h if the PCA9665 lost the arbitration

Table 26.

I2CCON initialization (Byte mode)

Bit

Symbol

ENSIO

STA

STO

reserved reserved

MODE

Value

1000

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