PCA9665D datasheet(23/91 Pages) PHILIPS

23 / 91 page

PCA9665_2

Product data sheet

Rev. 02 — 7 December 2006

23 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I2C-bus controller

(1) See Table 28.

(2) Deﬁned state when a single byte is received and an ACK is sent (AA = 1).

(3) Deﬁned state when a single byte is received and a NACK is sent (AA = 0).

(4) Master Transmitter Byte mode is entered when MODE = 0. Master Transmitter Buffered mode is entered when MODE = 1.

Fig 8.

Format and states in the Master Receiver Byte mode (MODE = 0)

08h

SLA

DATA

40h

50h

F8h

10h

SLA

to Master Transmitter mode

entry = MT(4)

48h

F8h

002aab025

38h

other MST

continues

A or A

38h

other MST

continues

other MST

continues

successful

reception from

a Slave Transmitter

next transfer started with a

repeated START condition

Not Acknowledge received after

the slave address

arbitration lost in slave address

or Acknowledge bit

arbitration lost and addressed as slave

This number (contained in I2CSTA) corresponds

to a defined state of the I2C-bus.(1)

DATA

any number of data bytes and

their associated Acknowledge bits

from master to slave

from slave to master

DATA

58h

(2)

(3)

B0h

68h

to corresponding states in Slave Transmitter mode

to corresponding states in Slave Receiver mode

D8h

to corresponding states in Slave Receiver mode (General Call)

PCA9665D Datasheet(PDF) 23 Page - NXP Semiconductors

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