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MCS7840
USB-2.0 to Four Serial Ports
Page 12
Rev.
1.2
FIFO Control Register (FCR):
The FCR controls the UART behavior in various modes.
Register:
FCR
Description:
FIFO Control Register
Offset:
2
Permissions:
Write
Access Condition:
Default Value:
0x00
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
RHR Trigger Level
Reserved
Reserved
Flush
THR
Flush
RHR
Enable
FIFOs
Bit
Description
Operation
0
Enable FIFO Mode
Logic 0: Byte Mode
Logic 1: FIFO Mode
1
Flush RHR
Logic 0: No change
Logic 1: Flushes the contents of RHR, This is operative
only in FIFO mode. The RHR is automatically
flushed whenever changing between Byte Mode
and FIFO Mode. The bit will return to zero after
clearing the FIFO.
2
Flush THR
Logic 0: No change
Logic 1: Flushes the content of the THR, in the same
manner as FCR[1] does the RHR
3
Reserved
Reserved
[5:4]
Reserved
Reserved
[7:6]
RHR Trigger Level
See Table Below
In 550 Mode, the receiver FIFO trigger levels are
defined by FCR[7:6].
The interrupt trigger level & flow control trigger level
where appropriate are defined by L2 in the table.
L1 defines a lower flow control trigger level. The two
trigger levels used together introduce a hysteresis
element into the hardware RTS/CTS flow control.
In Byte Mode (450 Mode) trigger levels are all set to 1.
FCR[7:6]
550 Mode (FIFO = 16)
L1
L2
2’b00
1
1
2’b01
1
4
2’b10
1
8
2’b11
1
14
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