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GL843 Datasheet(PDF) 29 Page - GENESYS LOGIC |
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GL843 Datasheet(HTML) 29 Page - GENESYS LOGIC |
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29 / 84 page ![]() GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 29 0 Enable clock 1 and 2 under CCD TG position as illustrated. 0 CTRLDIS 1 Disable CCD CP & RS signals under CCD TG position as illustrated. 0 Enable CCD CP & RS signals under CCD TG position as illustrated. Offset 17h ……………………………………………..…………..……….……. Default value = 8’h14 TGMODE1 TGMODE0 TGW5 TGW4 TGW3 TGW2 TGW1 TGW0 R/W R/W R/W R/W R/W R/W R/W R/W 7-6 TGMODE[1:0] To set CCD TG mode. 00 normal CCD TG type. 01 CCD TG control with dummy line. 10 CCD TG control with dummy lines for transparency scanning type. 11 reserved for ASIC simulation. 5-0 TGW[5:0] To set CCD TG plus width (in pixel time). Note: It cannot be programmed to logic zero. Offset 18h ……………………………………………..…………..……..………. Default value = 8’h00 CNSET DCKSEL1 DCKSEL0 CKTOGGLE CKDELAY1 CKDELAY0 CKSEL1 CKSEL0 R/W R/W R/W R/W R/W R/W R/W R/W 7 CNSET 0 Select TG and clock to be non-Canon CIS style. 1 Select TG and clock to be Canon CIS style. 6-5 DCKSEL1[1:0] 00 Speed 1: one CCD clock per system pixel time in shifting dummy lines. 01 Speed 2: two CCD clock per system pixel time in shifting dummy lines. 10 Speed 3: three CCD clock per system pixel time in shifting dummy lines. |
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