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GL843 Datasheet(PDF) 30 Page - GENESYS LOGIC

Part # GL843
Description  High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
PDF  84 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL843 Datasheet(HTML) 30 Page - GENESYS LOGIC

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GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 30
11
Speed 4: four CCD clock per system pixel time in shifting dummy lines.
4 CKTOGGLE
0
One cycle per pixel.
1
Half cycle per pixel for CCD clock 1 & 2.
3-2 CKDELAY[1:0] 00
No delay
01
Delay one system clock for CCD Clock 1/2.
10
Delay two systems clock for CCD Clock 1/2.
11
Delay three systems clock for CCD Clock 1/2.
1-0 CKSEL[1:0]
00
Speed 1: one CCD clock per system pixel time in capturing image.
01
Speed 2: two CCD clock per system pixel time in capturing image.
10
Speed 3: three CCD clock per system pixel time in capturing image.
11
Speed 4: four CCD clock per system pixel time in capturing image.
Note: Speed limitation of CCD clock in different scanning modes:
1. SCANMOD=0,1 : 12 clocks/pixel
a. toggle CCD : supports speed 1,2,3,4.
b. non-toggle CCD : supports speed 1,2,3.
2. SCANMOD=2
: Reserved.
3. SCANMOD=3
: Reserved.
4. SCANMOD=4
: Reserved.
5. SCANMOD=5
: Reserved.
6. SCANMOD=6
: 18 clocks/pixel
a. toggle CCD : supports speed 1,2,3.
b. non-toggle CCD : supports speed 1,2,3,4.
7. SCANMOD=7
: 16 clocks/pixel
a. toggle CCD : supports speed up 1,2,4.
b. non-toggle CCD : supports speed 1,2,4.
Note: Toggle CCD à
CCD which can output one pixel in one half cycle of CCD clock.
Non-toggle CCD à CCD which always output one pixel in one CCD clock cycle.
Offset 19h ……………………………………………..…………….…….……. Default value = 8’h00
EXPDMY7 EXPDMY6 EXPDMY5 EXPDMY4 EXPDMY3 EXPDMY2 EXPDMY1 EXPDMY0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 EXPDMY[7:0] To set exposure time of dummy lines (unit = 256 pixels time) or CIS LED
turn-on tme.
CIS SP
CIS LED
EXPDMY for turn on
EXPR/EXPG/EXPB for turn off
Note: It cannot be programmed to logic zero.
Offset 1Ah ……..……………………………………..…………..……………. Default value = 8’h00
TGLSW2
TGLSW1
MANUAL3 MANUAL1
CK4INV
CK3INV
LINECLP
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
7 TGLSW2
Set CCD SW2 output.
6
TGLSW1
Set CCD SW1 output.
5 MANUAL3
0
CCD Clock 3,Clock4 automatic output.
1
CCD Clock 3,Clock4 manual output.
4 MANUAL1
0
CCD Clock 1,Clock2 automatic output.
1
CCD Clock 1,Clock2 manual output.



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