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GL843 Datasheet(PDF) 31 Page - GENESYS LOGIC |
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GL843 Datasheet(HTML) 31 Page - GENESYS LOGIC |
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31 / 84 page ![]() GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 31 3 CK4INV 0 Don’t reverse. 1 To reverse CCD Clock4. 2 CK3INV 0 Don’t reverse. 1 To reverse CCD Clock 3. 1 LINECLP 0 To select CCD pixel clamping. 1 To select CCD line clamping. 0 RESERVED - Offset 1Bh ……..……………………………………..…………..……..……..…. Default value = 8’h00 GRAYSET CHANSEL BGRENB ICGENB ICGDLY3 ICGDLY2 ICGDLY1 ICGDLY0 R/W R/W R/W R/W R/W R/W R/W R/W 7 GRAYSET 0 Select single channel output. 1 Select two channel output. 6 CHANSEL 0 Fast true gray latch is 2 and 3 position. 1 Fast true gray latch is 1 and 2 position. 5 BGRENB 0 The order is R-G-B. 1 The order of latching A/D data is B-G-R. 4 ICGENB 0 To disable ICG control. 1 To enable CCD shutter control signal ICG. 3-0 ICGDLY[3:0] CCD ICG delay for rising/falling edge. Offset 1Ch ……..……………………………………..…………..…....………. Default value = 8’h00 CK4MTGL CK3MTGL CK1MTGL CKAREA MTLWD TGTIME2 TGTIME1 TGTIME0 R/W R/W R/W R/W R/W R/W R/W R/W 7 CK4MTGL 0 Disable toggle function in CCD clock 4. 1 Enable toggle function in CCD clock 4. 6 CK3MTGL 0 Disable toggle function in CCD clock 3. 1 Enable toggle function in CCD clock 3. 5 CK1MTGL 0 Disable toggle function in CCD clock 1 & 2. 1 Enable toggle function in CCD clock 1 &2. 4 CKAREA 0 This function is disabled. 1 CCD clock speed depends on CKSEL in scan area and DCKSEL in non-scan area. 3 MTLWD 0 Set the watchdog time-out as WDTIME[3:0]. 1 Set the watchdog time-out as WDTIME[3:0] * 2. 2-0 TGTIME[2:0] CCD line period selection. 000 1*LPERIOD(Reg38,Reg39) 001 2*LPERIOD 010 4*LPERIOD 011 8*LPERIOD 100 16*LPERIOD 101 32*LPERIOD 110 Reserved. 111 Reserved. |
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