MPC8280 datasheet(251/1386 Pages) FREESCALE

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External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

6-9

PSDAMUX

PGPL5

60x bus SDRAM address multiplexer—This output pin controls the 60x SDRAM address

multiplexer when the MPC8280 is in external master mode.

60x bus UPM general purpose line 5—One of six general purpose output lines from UPM. The

values and timing of this pin is programmed in the UPM.

LWE[0–3]

LSDDQM[0–3]

LBS[0–3]

PCI_CFG[0-3]

Local bus write enable—The write enable pins are outputs of the Local bus GPCM. These pins

select specific byte lanes for write operations.

Local bus SDRAM DQM—The DQM pins are outputs of the SDRAM control machine. These pins

select specific byte lanes of SDRAM devices.

Local bus UPM byte select—The byte select pins are outputs of the UPM in the memory

controller. They are used to select specific byte lanes during memory operations. The timing of

these pins is programmed in the UPM. The actual driven value depends on the address and size

of the transaction and the port size of the accessed device.

PCI Configuration—In PCI mode, PCI_CFG[0-3] configure the PCI bridge to Host or agent and

control the PCI arbiter operation:

• PCI_CFG[0] is PCI_HOST, when High enables the PCI bridge for Agent operation, when Low

enables the PCI as Host.

• PCI_CFG[1] is PCI_ARB_EN, when Low enables the PCI internal arbiter logic, when High

disables the internal arbiter logic (and an external arbiter should be used).

• PCI_CFG[2] is the DLL_Enable. In PCI mode, this pin should be pulled high externally in order

to use the DLL.

• PCI_CFG[3] is reserved and should be pulled high externally.

LSDA10

LGPL0

PCI_MODCK_H0

Local bus SDRAM A10—Output from the 60x bus SDRAM controller. Is part of the address when

a row address is driven and is part of the command when a column address is driven.

Local bus UPM general purpose line 0—This is one of six general purpose output lines from

UPM. The values and timing of this pin is programmed in the UPM.

PCI MODCK_H0—In PCI mode, defines the operating mode of internal clock circuits.

LSDWE

LGPL1

PCI_MODCK_H1

Local bus SDRAM write enable—Output from the local bus SDRAM controller. Should be

connected to the WE inputs of the SDRAMs.

Local bus UPM general purpose line 1—This is one of six general purpose output lines from

UPM. The values and timing of this pin is programmed in the UPM.

PCI MODCK_H1—In PCI mode, defines the operating mode of internal clock circuits.

LOE

LSDRAS

LGPL2

PCI_MODCK_H2

Local bus output enable—The output enable pin is an output of the Local bus GPCM. Controls

the output buffer of memory devices during read operations.

Local bus SDRAM RAS—Output from the Local bus SDRAM controller. Should be connected to

the SDRAM RAS input.

Local bus UPM general purpose line 2—This is one of six general purpose output lines from

UPM. The values and timing of this pin is programmed in the UPM.

PCI MODCK_H2—In PCI mode, defines the operating mode of internal clock circuits.

Table 6-1. External Signals (continued)

Signal

Description

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