MPC8280 datasheet(18/1386 Pages) FREESCALE

18 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

xviii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

Chapter 10

Clocks and Power Control

10.1

MPC8280 Clock Block Diagram ................................................................................... 10-1

10.1.1

Main PLL................................................................................................................... 10-1

10.1.2

Core PLL.................................................................................................................... 10-2

10.1.3

Skew Elimination....................................................................................................... 10-2

10.1.4

Dividers...................................................................................................................... 10-2

10.1.5

Internal Clock Signals................................................................................................ 10-2

10.1.6

PCI Bridge as an Agent Operating from the PCI System Clock ............................... 10-4

10.1.7

PCI Bridge as a Host Generating the PCI System Clock .......................................... 10-4

10.2

External Clock Inputs .................................................................................................... 10-5

10.3

PLL Pins ....................................................................................................................... 10-5

10.4

System Clock Control Register (SCCR)........................................................................ 10-6

10.5

System Clock Mode Register (SCMR).......................................................................... 10-7

10.5.1

Core PLL Configurations........................................................................................... 10-8

10.6

Clock Configuration Modes........................................................................................... 10-9

Chapter 11

Memory Controller

11.1

Features .......................................................................................................................... 11-3

11.2

Basic Architecture.......................................................................................................... 11-4

11.2.1

Address and Address Space Checking....................................................................... 11-7

11.2.2

Page Hit Checking ..................................................................................................... 11-8

11.2.3

Error Checking and Correction (ECC) ...................................................................... 11-8

11.2.4

Parity Generation and Checking ................................................................................ 11-8

11.2.5

Transfer Error Acknowledge (TEA) Generation ....................................................... 11-8

11.2.6

Machine Check Interrupt (MCP) Generation ............................................................ 11-9

11.2.7

Data Buffer Controls (BCTLx and LWR) ................................................................. 11-9

11.2.8

Atomic Bus Operation ............................................................................................... 11-9

11.2.9

Data Pipelining ......................................................................................................... 11-9

11.2.10

External Memory Controller Support ...................................................................... 11-10

11.2.11

External Address Latch Enable Signal (ALE) ......................................................... 11-10

11.2.12

ECC/Parity Byte Select (PBSE) .............................................................................. 11-10

11.2.13

Partial Data Valid Indication (PSDVAL) ..................................................................11-11

11.2.14

BADDR[27:31] Signal Connections ....................................................................... 11-12

11.3

Register Descriptions ................................................................................................... 11-12

11.3.1

Base Registers (BRx) ............................................................................................... 11-13

11.3.2

Option Registers (ORx) ........................................................................................... 11-15

11.3.3

60x SDRAM Mode Register (PSDMR) .................................................................. 11-20

MPC8280 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL