MPC8280 datasheet(65/1386 Pages) FREESCALE

65 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

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Figures

Figure

Number

Title

Page

Number

35-2

TC Layer Block Diagram...................................................................................................... 35-3

35-3

TC Cell Delineation State Machine ...................................................................................... 35-4

35-4

HEC: Receiver Modes of Operation ..................................................................................... 35-5

35-5

TC Layer Mode Registers (TCMODEx)............................................................................... 35-7

35-6

Cell Delineation State Machine Registers (CDSMRx) ......................................................... 35-8

35-7

TC Layer Event Registers (TCERx) ..................................................................................... 35-9

35-8

TC Layer General Event Register (TCGER) ...................................................................... 35-10

35-9

TC Layer General Status Register (TCGSR) ...................................................................... 35-11

35-10

TC Operation in FCC External Rate Mode......................................................................... 35-14

35-11

TC Operation in FCC Internal Rate Mode (Sub Rate Mode) ............................................. 35-14

35-12

Example of Serial ATM Application .................................................................................. 35-15

36-1

Ethernet Frame Structure ...................................................................................................... 36-1

36-2

Ethernet Block Diagram ....................................................................................................... 36-2

36-3

Connecting the MPC8280 to Ethernet .................................................................................. 36-4

36-4

Connecting the MPC8280 to Ethernet (RMII)...................................................................... 36-5

36-5

Ethernet Address Recognition Flowchart ........................................................................... 36-16

36-6

FCC Ethernet Mode Registers (FPSMRx) .......................................................................... 36-20

36-7

Ethernet Event Register (FCCE)/Mask Register (FCCM).................................................. 36-22

36-8

Ethernet Interrupt Events Example ..................................................................................... 36-23

36-9

Fast Ethernet Receive Buffer (RxBD) ................................................................................ 36-24

36-10

Ethernet Receiving Using RxBDs....................................................................................... 36-26

36-11

Fast Ethernet Transmit Buffer (TxBD) ............................................................................... 36-27

37-1

HDLC Framing Structure...................................................................................................... 37-2

37-2

HDLC Address Recognition Example .................................................................................. 37-5

37-3

HDLC Mode Register (FPSMR)........................................................................................... 37-8

37-4

FCC HDLC Receiving Using RxBDs................................................................................. 37-10

37-5

FCC HDLC Receive Buffer Descriptor (RxBD) ................................................................ 37-11

37-6

FCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 37-12

37-7

HDLC Event Register (FCCE)/Mask Register (FCCM) .................................................... 37-14

37-8

HDLC Interrupt Event Example ......................................................................................... 37-16

37-9

FCC Status Register (FCCS)............................................................................................... 37-16

38-1

In-Line Synchronization Pattern ........................................................................................... 38-2

38-2

Sending Transparent Frames between MPC8280s ............................................................... 38-4

39-1

SPI Block Diagram ............................................................................................................... 39-1

39-2

Single-Master/Multi-Slave Configuration ............................................................................ 39-3

39-3

Multi-Master Configuration .................................................................................................. 39-5

39-4

SPMODE—SPI Mode Register ............................................................................................ 39-6

39-5

SPI Transfer Format with SPMODE[CP] = 0....................................................................... 39-7

39-6

SPI Transfer Format with SPMODE[CP] = 1....................................................................... 39-8

39-7

SPIE/SPIM—SPI Event/Mask Registers .............................................................................. 39-9

39-8

SPCOM—SPI Command Register ..................................................................................... 39-10

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