MPC8280 datasheet(522/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-102

Freescale Semiconductor

There are two types of external bus masters:

•

Any 60x-compatible device with a 64-bit data bus, such as an MPC603e, MPC604e, MPC750, or

an MPC2605 (L2 cache) in copy-back mode

•

MPC8280

Both of these external bus master types can access a slave MPC8280’s internal registers and dual-port

RAM. They can also use the slave’s memory controller to access memory devices on the 60x bus. An

external master has access to the slave’s local bus via the slave’s 60x-to-local bus bridge.

11.9.1

60x-Compatible External Masters (non-MPC8280)

A non-MPC8280 external master can perform only 64-bit port accesses when using a slave MPC8280’s

memory controller for memory devices assigned to the 60x bus. Also, ECC or RMW-parity are not

supported.

For 60x bus compatibility, the following connections should be observed:

•

MPC8280’s TSIZ[1–3] should be connected to the external master’s TSIZ[0–2]

•

MPC8280’s TSIZ[0] should be pulled down

•

MPC8280’s PSDVAL should be pulled up

11.9.2

MPC8280 External Masters

An MPC8280 external master is a 60x-compatible master with additional functionality. As described in

the following, it has fewer the restrictions than other 60x-compatible masters:

•

Any port size is allowed

•

ECC and RMW-parity are supported

11.9.3

Extended Controls in 60x-Compatible Mode

In 60x-compatible mode, the memory controller provided extended controls for the glue logic. The

extended control consists of the following:

•

Memory address latch (ALE) to latch the 60x address for memory use

•

The address multiplex pin (GPL5/SDAMUX), which controls external multiplexing for DRAM

and SDRAM devices

•

LSB address pins (BADDR[27–31]) for incrementing memory addresses

•PSDVAL as a termination to a partial transaction (such as port-size beat access).

11.9.4

Address Incrementing for External Bursting Masters

BADDR[27–31] should be used to generate addresses to memory devices for burst accesses. In

60x-compatible mode, when a master initiates an external bus transaction, it reflects the value of A[27–31]

on the first clock cycle of the memory access. These signals are latched by the memory controller and on

subsequent clock cycles, BADDR[27–31] increments as programmed in the UPM or after each data beat

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