TMPR3911 datasheet(43/462 Pages) TOSHIBA

43 / 462 page

Chapter 1 TMPR3911/12 Overview

1-1

TMPR3911/12 Overview

1.1

Overview

The TMPR3911/12 is the single-chip, integrated digital ASSP for the Personal Digital Assistants (PDA).

Figure 1.1.1 shows a block diagram of the overall PDA system. The TMPR3911/12 consists of the PDA

system support logic, integrated with an embedded TX39/H Processor core designed by TOSHIBA.

The TMPR3911/12 consists of a TX39/H Processor core with 4 Kbytes of instruction cache memory and 1

Kbyte of data cache memory, plus integrated functions for interfacing to numerous system components and

external

I/O

modules.

The

TX39/H

Processor

core

also

augmented

with

single-cycle

multiply/accumulate module to allow integrated DSP functions, such as a software modem for high-

performance standard data and fax protocols. The TMPR3911/12 also contains multiple DMA channels and

a high-performance and flexible Bus Interface Unit (BIU) for providing an efficient means for transferring

data between external system memory, cache memory, the Processor core, and external I/O modules. The

types of external memory devices supported include dynamic random access memory (DRAM), synchronous

dynamic random access memory (SDRAM), static random access memory (SRAM), Flash memory, read-

only memory (ROM), and expansion cards (PCMCIA and/or MagicCard). The TMPR3911/12 also contains

a System Interface Module (SIM) containing integrated functions for interfacing to numerous external I/O

modules such as liquid crystal displays (LCD’s), the TC35143 (which handles most of the analog functions

of the system, including sound and telecom codecs and touchscreen ADC), ISDN/high-speed serial, infrared,

wireless peripherals, Magicbus, etc. Lastly, The TMPR3911/12 contains support for implementation of

power management for PDA system, whereby various TMPR3911/12 internal modules and external

subsystems can be individually (under software control) powered up and down. The TMPR3911/12 contains

the following overall features:

•

high level of integration on a single chip, small board space, low pin count, low power, and high

performance

•

Plastic LQFP208-pin package (TMPR3912AU-92)

FBGA 217-pin package (TMPR3912XB-92)

Plastic LQFP176-pin package (TMPR3911BU)

FBGA177-pin package (TMPR3911BXB)

•

32-bit TX39/H Processor core, cache memory, multiply-accumulate module, multi-channel DMA

controller, bus interface unit and memory controller, power management, and other peripheral

subsystems all on a single integrated chip

•

minimal number of inter-chip connections

•

Maximum operation frequency: 58 MHz (TMPR3911BU and TMPR3911BXB)

92 MHz (TMPR3912AU-92 and XB-92)

•

low power consumption

•

entire TMPR3911/12 operation is 3.3 V (in case of TMPR3911BU/BXB, I/O: 3.3 V,

internal: 2.6 V)

•

real-time clock based on 32.768 kHz reference

•

Processor core clock stop state for low standby current

•

power-down modes for individual internal peripheral modules

TMPR3911 Datasheet(PDF) 43 Page - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 43 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL