TMPR3911 datasheet(67/462 Pages) TOSHIBA

67 / 462 page

Chapter 2 Pin Descriptions

2-13

2.2.13

Endian Pin

ENDIAN:

INPUT

This pin is used to select the endianness. The high level input sets the endianness to the big

endian. The low level input sets the endianness to the little endian.

2.2.14

Test Pins

TESTAIU:

INPUT

If this pin is set to low during reset, ROM data bus width will be 16 bits wide.

If this pin is set to high during reset, ROM data bus width will be 32 bits wide.

When the DREQ* signal is asserted to request external arbitration, this pin must be set to low.

TESTCPU:

INPUT

Connect to GND.

TESTIN:

INPUT

Connect to GND.

2.2.15

Spare Pins

NC3-1:

NO CONNECT

These pins are reserved for future use and should be left unconnected.

2.2.16

Power Supply Pins

VDD:

+3.3 V

These pins are the power pins.

(In case of TMRP3912AU-92 and TMRP3912XB-92)

VSS:

GND

These pins are the ground pins for the TMPR3911/12.

VDDH:

+3.3 V

These pins are the power pins for I/O.

(In case of TMPR3911BU and TMPR3911BXB)

VDDL:

+2.6 V

These pins are the power pins for internal logic.

(In case of TMPR3911BU and TMPR3911BXB)

VDD (PLL):

+2.6 V

These pins are the power pins for PLL.

(In case of TMPR3911BU and TMPR3911BXB)

VSS (PLL):

GND

These pins are the ground pins for PLL.

(In case of TMPR3911BU and TMPR3911BXB)

TMPR3911 Datasheet(PDF) 67 Page - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 67 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL