TMPR3911 datasheet(9/462 Pages) TOSHIBA

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Table of Contents

11.3.1

Block Diagram ......................................................................................................................................11-4

11.3.2

Transmitter ............................................................................................................................................11-5

11.3.3

Receiver.................................................................................................................................................11-6

11.3.4

Control Logic ........................................................................................................................................11-7

11.3.5

DMA Address Generation.....................................................................................................................11-9

11.3.6

Related Interrupts ................................................................................................................................11-10

11.4

Magicbus Registers..................................................................................................................................... 11-11

11.4.1

Magicbus Control 1 Register............................................................................................................... 11-11

11.4.2

Magicbus Control 2 Register...............................................................................................................11-13

11.4.3

Magicbus DMA Control 1 Register ....................................................................................................11-14

11.4.4

Magicbus DMA Control 2 Register ....................................................................................................11-14

11.4.5

Magicbus DMA Count ........................................................................................................................11-14

11.4.6

Magicbus Transmit Holding Register..................................................................................................11-15

11.4.7

Magicbus Receive Holding Register ...................................................................................................11-15

12. Power Module .......................................................................................................................................................12-1

12.1

Overview ......................................................................................................................................................12-1

12.1.1

System Power Control Overview ..........................................................................................................12-1

12.1.2

Power State Transition Diagram............................................................................................................12-2

12.1.3

Power Supply Lines in the System........................................................................................................12-3

12.1.4

Related Pins...........................................................................................................................................12-4

12.2

Description ...................................................................................................................................................12-5

12.2.1

Power On Reset.....................................................................................................................................12-5

12.2.2

The 1

st Power Up...................................................................................................................................12-6

12.2.3

Power Down..........................................................................................................................................12-7

12.2.4

Power Up...............................................................................................................................................12-8

12.2.5

Stop CPU...............................................................................................................................................12-9

12.2.6

Forced Shutdown.................................................................................................................................12-10

12.2.7

Memory Power Down .........................................................................................................................12-10

12.2.8

Stop Timer...........................................................................................................................................12-10

12.2.9

Power Module Interrupts.....................................................................................................................12-11

12.3

Power Registers ..........................................................................................................................................12-12

12.3.1

Power Control Register .......................................................................................................................12-12

13. SIB Module ...........................................................................................................................................................13-1

13.1

Overview ......................................................................................................................................................13-1

13.1.1

Related Pins...........................................................................................................................................13-2

13.2

Block Diagram..............................................................................................................................................13-3

13.2.1

Holding and Shift Registers ..................................................................................................................13-4

13.2.2

Clock and Sync Generation...................................................................................................................13-4

13.3

Interface Requirements.................................................................................................................................13-6

13.3.1

Frame Structure .....................................................................................................................................13-6

13.3.2

Timing Requirements ............................................................................................................................13-6

13.3.3

Configurations.......................................................................................................................................13-7

13.3.4

Sample Rates .........................................................................................................................................13-8

13.3.5

Enable/Disable Sequencing.................................................................................................................13-10

13.3.6

Data Formats .......................................................................................................................................13-11

13.3.7

Subframe Formats ...............................................................................................................................13-12

13.4

DMA Address Generation ..........................................................................................................................13-15

13.5

Related Interrupts .......................................................................................................................................13-17

TMPR3911 Datasheet(PDF) 9 Page - Toshiba Semiconductor

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