TMPR3911 datasheet(79/462 Pages) TOSHIBA

79 / 462 page

Chapter 2 Pin Descriptions

2-25

2.4.3

Pin Assignment (in case of TMPR3911BXB)

Table 2.4.6 Pin Assignment (1/2)

NO.

I/O

Signal Name

NO.

I/O

Signal Name

NO.

I/O

Signal Name

I/O

D[1] (D[25])

SIBDIN

I/O

A[3]



VDDH



VCC3

I/O

D[0] (D[24])

I/O

IO[6]

BC32K

I/O

D[3] (D[27])

IRIN

C32KIN

I/O

D[5] (D[29])

TXD

VIDDONE

I/O

D[9] (D[17])

DCLKOUT



VSS

I/O

D[12] (D[20])



VDDH

I/O

A[4]



VDDH

CAS1* (CAS2*)C8

I/O

A[6]



VDDH



VSS

I/O

A[5]

SIBSYNC



VDDL

C32KOUT

SIBIRQ

I/O

D[10] (D[18])

TESTAIU

I/O

IO[5]

I/O

D[14] (D[22])



VSS

CHIDIN

I/O

MIOX[1]



VDDH

CHIDOUT

I/O

MBUSDATA

I/O

A[9]

I/O

IO[4]



VDDL

I/O

A[7]

DQML (DQMH)

SIBSCLK

I/O

A[8]



VSS



VDDH

I/O

D[2] (D[26])

CARDET

PWRCS

I/O

D[6] (D[30])

I/O

IO[3]

PWROK

I/O

D[8] (D[16])

IROUT

PWRINT

I/O

D[11] (D[19])

CAS0* (CAS3*)R9

ONBUTN

ENDIAN

CAS2* (CAS1*)A10

WE*

MBUSINT

CAS3* (CAS0*)

B10

I/O

A[10]



VSS

RAS1*

C10

I/O

A[11]



VSS



D10

I/O

A[12]

SIBDOUT



VDDL

M10



VDDL

I/O

MIOX[0]

I/O

IO[2]

N10

PON*

I/O

CHICLK

SPICLK

P10

CPURES*

I/O

CHIFS

RXPWR

R10

DISPON

RXD

RAS0*

A11



VDDL

DQMH (DQML)

DCS0*

B11

ALE

DCLKIN



VSS

C11

DREQ*

DCKE

I/O

A[0]

D11

DGRNT*

I/O

D[4] (D[28])

SPIOUT

M11

FRAME

I/O

D[7] (D[31])

TESTCPU

N11

LOAD



VSS

TESTIN

P11

I/O

D[15] (D[23])

SPIIN

R11



VSS

I/O

D[13] (D[21])

I/O

A[1]

A12



VDDH

I/O

MBUSCLK

I/O

A[2]

B12



VSS

SIBMCLK



VDDL

C12

RD*

<NOTE>

(1)

* Active-low signal

(2)

( ) indicates the signal name in the little endian mode

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