TMPR3911 datasheet(91/462 Pages) TOSHIBA

91 / 462 page

Chapter 3 CPU Module

3-7

3.3.6

TLB

The TLB in the TX39/H core is based on R3000.

The differences between the TLB in the TX39/H core and the TLB in the R3000 are as follows.

(1)

Kseg2 TLB Mapping Area

The address from 0xFF00_0000 to 0xFFFE_FFFF in Kseg2 is a reserved area.

The following table shows the address mapping of the TX39/H core.

Segment

Virtual Address

Physical Address

Cacheable

Kseg2

0xFFFF_FFFF

0xFFFF_0000

TLB Mapped

Yes

Reserved

0xFFFE_FFFF

0xFF00_0000

0xFFFE_FFFF

0xFF00_0000

Kseg2

0xFEFF_FFFF

0xC000_0000

TLB Mapped

Yes

Kseg1

0xBFFF_FFFF

0xA000_0000

0x1FFF_FFFF

0x0000_0000

Kseg0

0x9FFF_FFFF

0x8000_0000

0x1FFF_FFFF

0x0000_0000

Yes

Kuseg

0x7FFF_FFFF

0xC000_0000

TLB Mapped

Yes

(2) Multi-hit Detection

Even though some of virtual address in the TLB entries are same, the TX39/H core does not

detect multi-hit while the R3000 detects it.

(3) The Number of TLB Entries

The TX39/H core has 32 TLB entries while the R3000 has 64 TLB entries.

3.3.6.1

Memory Management System

The TX39/H provides a full-featured memory management unit (MMU) utilizing an on-chip

Translation Lookaside Buffer (TLB) to provide very fast virtual memory accesses. This chapter

describes the operation of the TLB and the CP0 registers that provide the software interface to the

TLB. The memory mapping scheme supported by the TX39/H to translate virtual addresses to

physical addresses is also described in detail.

TMPR3911 Datasheet(PDF) 91 Page - Toshiba Semiconductor

TMPR3911 Datasheet(HTML) 91 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL