TMPR4938 datasheet(183/716 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-9

8.3.5

Memory-Memory Copy Mode

It is possible to copy memory from any particular address to any other particular address when in the

Memory-Memory Copy mode.

Set the DMA Channel Control Register (DMCCRn) as follows.

•

DMCCRn.EXTRQ

= 0: Memory Transfer mode

•

DMCCRn.SNGAD

= 0: Dual Address mode

Furthermore, when in the Memory-Memory Copy mode it is possible to set the interval for requesting

ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control

Refer to “8.3.8 Dual Address Transfer” for information regarding the setting of other registers.

8.3.6

Memory Fill Transfer Mode

When in the Memory Fill Transfer mode, double word data set in the DMA Memory Fill Data

(DMSARn). This data can be used for initializing the memory, etc.

Set the DMA Channel Control Register (DMCCRn) as follows.

•

DMCCRn.EXTRQ = 0: Memory transfer mode

•

DMCCRn.SNGAD

= 1: Single Address Transfer

•

DMCCRn.MEMIO = 0: Transfer from I/O to memory

In addition, when in the Memory Fill Transfer mode, it is possible to set the interval for requesting

ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control

Refer to “8.3.7 Single Address Transfer” for information regarding the setting of other registers.

By using this function together with the memory Write function that writes to multiple SDRAM

Controller memory channels simultaneously (refer to Section 9.3.4), it is possible to initialize memory

even more efficiently.

8.3.7

Single Address Transfer

This section explains register settings during Single Address transfer (DMCCRn.SNGAD = 1). This

applies to the following DMA Transfer modes.

•

External I/O (Single Address) Transfer

•

Memory Fill Transfer

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