TMPR4938 datasheet(186/716 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-12

8.3.8

Dual Address Transfer

This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This

applies to the following DMA transfer modes.

•

External I/O (Dual Address) transfer

•

Internal I/O DMA transfer

•

Memory-Memory Copy transfer

8.3.8.1

Channel Register Settings During Dual Address Transfer

Table 8.3.3 shows restrictions of the Channel Register settings during Dual Address transfer. If

these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit

(CFERR) of the DMA Channel Status Register (DMCSRn) is set, and DMA transfer is not

performed.

If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the

transfer setting size is 8 bytes or larger, then a value will be set in the DMA Source Address

If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the

transfer size is 2 bytes or larger, set the DMA Source Address Register (DMSARn) as follows:

•

If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented.

•

If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented.

•

If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits

complemented.

Likewise, if the setting of the DMA Destination Address Increment Register (DMDAIRn) is

negative and the transfer size is 2 bytes or larger, set the DMA Destination Address Register

(DMDARn) as follows:

•

If the transfer size is 2 bytes, set the DMDARn with the low-order 1 bit complemented.

•

If the transfer size is 4 bytes, set the DMDARn with the low-order 2 bits complemented.

•

If the transfer size is 8 bytes or larger, set the DMDARn with the low-order 3 bits

complemented.

Example: When the transfer address is 0x0_0001_0000, the DMA Source Address

•

DMSAIRn setting is “0” or greater: 0x0_0001_0000

•

DMSAIRn setting is a negative value: 0x0_0001_0007

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