TMP93CS32F datasheet(105/180 Pages) TOSHIBA

105 / 180 page

TMP93CS32

2004-02-10

93CS32-103

Setting example: To output 2 ms one-shot pulse with 3 ms delay to the external trigger

pulse to TI4 pin

* Clock Condition

Clock gear: 1 (fc)

Prescaler clock: fFPH

Keep counting (Free running).

Main setting

Count with

φT1.

T4MOD

← − − 1 0 1 0 0 1

T4FFCR

← X X 0 0 0 0 1 0

Load the up counter value into CAP1 at the rise edge of TI4

pin input.

Clear TFF4 to zero.

Disable TFF4 inversion.

P4CR

← − − − 1 − − − 1

P4FC

← − X X 1 X X − X

Select P44 as the TO4 pin.

INTE45

← − − − − 1 10 0

INTET54

← 1 0 0 0 1 0 0 0

Enable INT4, and disable INTTR4 and INTTR5.

TRUN

← 1 X − 1 − − − −

Start timer 4.

Setting of INT4

TREG4

← CAP1 + 3 ms/φT1

TREG5

← TREG4 + 2 ms/φT1

T4FFCR

← X X − − 1 1 −−

Enable TFF4 inversion when the up counter value matches

TREG4 or TREG5.

INTET54

← 1 1 0 0 − − − −

Enable INTTR5.

Setting of INTTR5

T4FFCR

← X X − − 0 0 −−

Disable TFF4 inversion when the up counter value matches

TREG4 or TREG5.

INTET54

← 1 0 0 0 − − − −

Disable INTTR5.

X: Don’t care,

−: No change

When delay time is unnecessary, invert timer flip-flop TFF4 when the up counter

value is loaded into capture register 1 (CAP1), and set the CAP1 value (c) plus the

one-shot pulse width (p) to TREG5 when the interrupt INT4 occurs. The TFF4

inversion should be enabled when the up counter (UC4) value matches TREG5, and

disabled when generating the interrupt INTTR5.

TMP93CS32F Datasheet(PDF) 105 Page - Toshiba Semiconductor

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