TMP93CS32F datasheet(127/180 Pages) TOSHIBA

127 / 180 page

TMP93CS32

2004-02-10

93CS32-125

12. Signal generation timing

1) In I/O Interface mode

SCLK0 output mode

Immediately after rise of last SCLK0 signal

(See Figure 3.9.17.)

Timing for send

interrupt

generation

SCLK0 input mode

Immediately after rise (Rising mode) or fall (Falling mode) of

last SCLK0 signal

(See Figure 3.9.18.)

SCLK0 output mode

Immediately after final SCLK0 (When received data are

transferred to receive buffer 2 (SC0BUF))(See Figure 3.9.19.)

Timing for

receive interrupt

generation

SCLK0 input mode

Immediately after final SCLK0 (When received data are

transferred to receive buffer 2 (SC0BUF))(See Figure 3.9.20.)

2) In UART mode

Receive

Mode

9-Bit

8-Bit

+ Parity

8-Bit, 7-Bit

+ Parity, 7-Bit

Timing for interrupt

generation

Center of last bit (Bit8)

Center of last bit(parity bit)

Center of stop bit

Timing for framing

error generation

Center of stop bit

Timing for parity error

generation

−

Center of last bit

(parity bit)

Center of stop bit

Timing for overrun

error generation

Center of last bit (Bit8)

Center of last bit

(parity bit)

Center of stop bit

Note:

In 9-Bit and 8-Bit

+ Parity mode, interrupts coincide with the ninth bit pulse. Thus,

when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the

stop bit to be transferred) to allow checking for a framing error.

Send

Mode

9-Bit

8-Bit

+ Parity

8-Bit, 7-Bit

+ Parity, 7-Bit

Timing for interrupt

generation

Immediately before

stop bit sent

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TMP93CS32F Datasheet(PDF) 127 Page - Toshiba Semiconductor

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