TMP93CS32F datasheet(177/180 Pages) TOSHIBA

177 / 180 page

TMP93CS32

2004-02-10

93CS32-175

(2) Care points

, AM8/ AM16 pin

Fix these pins VCC unless changing voltage.

2. HALT mode (IDLE1)

When IDLE1 mode (oscillator operation only) is used, clear TRUN<PRRUN> to “0” to

stop prescaler before “HALT” instruction is executed.

3. Warm-up counter

The warm-up counter operates when STOP mode is released even if the system is using

an external oscillator. As a result, it takes warm-up time from inputting the releasing

request to outputting the system clock.

4. Programmable pull-up resistor

The programmable pull-up resistors can be turned ON/OFF by the program when the

ports are used as input ports. When the ports are used as outputs, they can not be selected

ON/OFF by the program.

The data registers (e.g. P6 register …) are used for the pull-up resistors ON/OFF.

Consequently, Read-modify-write instructions are prohibited.

5. Watchdog timer

The watchdog timer starts operation immediately after the reset is released. When the

watchdog timer is not used, disable it.

6. AD converter

The string register between VREFH and VREFL pins can be cut by a program to reduce

power consumption. When the Standby mode is used, disable the resistor using the

program before the “HALT” instruction is executed.

7. CPU (Micro DMA)

Only the “LDC cr, r”, “LDC r, cr” instructions can be used to access the control registers in

the CPU like the transfer source address register (DMASn).

8. POP SR instruction

Please execute POP SR instruction during DI condition.

9. Releasing the HALT mode by requesting an interruption

Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0)

which can release the HALT mode may not be able to do so if they are input during the

period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP

mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is

kept on hold internally.)

If another interrupt is generated after it has shifted to HALT mode completely, halt

status can be released without difficultly. The priority of this interrupt is compare with that

of the interrupt kept on hold internally, and the interrupt with higher priority is handled

first followed by the other interrupt.

TMP93CS32F Datasheet(PDF) 177 Page - Toshiba Semiconductor