Data Sheet

ADF5612

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 9 of 48

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 5, 7, 9, 11, 12, 14, 16, 18,

20, 22, 24 to 26, 30, 32, 36, 38,

40, 45, 47

GND

Negative Power Supply (Ground). Tie the GND pins directly to the ground pad.

2

RVDD

3.3V ± 5% Positive Power Supply for the Reference Circuitry. Short the RVDD pin to the other pins in the 3.3V power

supply group.

4

VDDLS

3.3V ± 5% Typical Power Supply for the Charge Pump Digital Section. VDDLS must be equal to VPPCP.

6

CP

Charge Pump Output. When enabled, this output provides the positive and negative output current magnitude (±ICP) to the

external loop filter. The output of the loop filter is connected to the VT pin to drive the internal VCO. Place the first pole of

the low-pass loop filter close to the CP pin if the loop filter path is electrically long.

8

VPPCP

3.3V ± 5% Typical Power Supply for Charge Pump. VPPCP must be equal to VDDLS.

10

AVDD

3.3V ± 5% Analog Supply. AVDD must be equal to DVDD.

13

CREG

Output of the On-Chip Regulator. Connect an external bypass decoupling capacitor of 220nF.

15

VCCPD

3.3V ± 5% Phase Detector Supply.

17

VCCPS

3.3V ± 5% Prescaler Supply.

19

SDO

Serial Data Output. Various other functions are available via an internal mulitplexer. In 3-wire mode (default mode), this

three-state CMOS pin remains in a high impedance state. In 4-wire readback mode, the SDO pin presents data from the

SPI during a read communication burst. When the CSB is de-asserted, SDO returns to a high impedance. Optionally,

attach a resistor of >1kΩ to prevent a floating output. See the MUXOUT section for more details.

21

VCCHF

3.3V ± 5% Power Supply for PLL RF Section. Place a decoupling capacitor as close as possible to this pin.

23

VDD1

3.3V ± 5% Bias for VCO Digital Logic.

27

NDIV_OUT

Complementary Output of Differential Frequency Divider. N = 1, 2, 4, 8, 16, 32, 64, or 128. A DC block is required, and a

broadband 100nF capacitor is recommended. Pin disabled upon power-up.

28

PDIV_OUT

Primary Output of Differential Frequency Divider. N = 1, 2, 4, 8, 16, 32, 64, or 128. A DC block is required, and a

broadband 100nF capacitor is recommended. Pin disabled upon power-up.

29

VDD3

3.3V ± 5% Differential Output Divider Supply.

31

RFOUT

RF Output (7300MHz to 8500MHz). RFOUT has an internal DC block, and an external DC block with a 100nF capacitor is

required.

33

VCOVCC

5.0V ± 5% VCO Power Supply.

34

VDD2

3.3V ± 5% VCO Calibration DAC Supply.

35

VPRST

Temperature Dependent, Calibration Preset. Decouple VPRST with a 470nF capacitor.

37

VT

VCO Tuning Port. Place the last pole of the low-pass filtered charge pump output close to the VT pin if the loop filter path

is electrically long.

39

VG

Gate Voltage Bypassing. Decouple VG to GND with a low effective series resistance (ESR), 10 µF capacitor.

41

SCK

Serial Port Clock. This CMOS input clocks the serial port input data on its rising edge.