Data Sheet

ADF5612

THEORY OF OPERATION

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Rev. 0 | 23 of 48

Serial Port

The SPI-compatible serial port provides control and monitoring

functionality. The CMOS_OV bit (Register 0x035, Bit 5) determines

if the logic high level for the SDO and SDIO SPI output pins is

3.3V or 1.8V. The SPI can be programmed to support several

different configurations in Register 0x000 and Register 0x001.

The SDO_ACTIVE bit (Register 0x000, Bit 3) determines if the

serial port is configured as a 3-wire or 4-wire SPI (see the timing

diagrams in Figure 2, Figure 3 and Figure 4.

The SPI register map can be programmed with single instructions,

as shown in Figure 49 and Figure 50, or in streaming mode, as

shown in Figure 51. Streaming mode allows for efficient data trans-

fer read or write cycles to multiple registers. Streaming mode allows

the user to program a bit stream composed of one register address

in the instruction header and data for that register address, which

is then followed by data in subsequent register addresses. The

ADDRESS_ASCENSION bit (Register 0x000, Bit 2) determines if

the subsequent register addresses are incremented or decrement-

ed. It is recommended to decrement the register addresses in

streaming mode (ADDRESS_ASCENSION = 0). The reason for this

recommendation is because REG0010 triggers the VCO calibration

and loading of all double buffers and, therefore, must be the last

SPI register written to. The SINGLE_INSTRUCTION bit (Register

0x001, Bit 7) disables streaming mode when it is set to 1. When

SINGLE_INSTRUCTION is set to 0, streaming mode is enabled.

Figure 49. Serial Interface, MSB First (LSB_FIRST = 0)

Figure 50. Serial Interface, LSB First (LSB_FIRST = 1)

Figure 51. Serial Interface, Recommended Streaming Mode (SINGLE_INSTRUCTION = 0) with Decrementing Registers (ADDRESS_ASCENCION = 0)