TMP88CU74F datasheet(59/132 Pages) TOSHIBA

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TMP88CU74

2003-02-17

88CU74-59

2.5

Divider Output (DVO )

Approximately 50% duty pulse can be output using the divider output circuit, which is useful

for piezoelectric buzzer drive. Divider output is from pin P13 ( DVO ). The P13 output latch

should be set to “1” and then the P13 should be configured as an output mode.

TBTCR

(00036H)

DVOEN

DVOCK

(DV7CK) (TBTEN)

(TBTCK)

(Initial value: 0

**0 0***)

DVOEN

Divider output enable/disable

0: Disable

1: Enable

NORMAL1/2, IDLE1/2 mode

DV7CK

= 0

DV7CK

= 1

DV1CK

= 0 DV1CK = 1 DV1CK = 0 DV1CK = 1

SLOW,

SLEEP

mode

fc/2

fs/2

fc/2

fs/2

fc/2

fs/2

DVOCK

Divider output ( DVO )

frequency selection [Hz]

fc/2

fs/2

R/W

Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz],

*: Don’t care

Figure 2.5.1 Divider Output Control Register

Example: 1.5 kHz pulse output (at fc = 12.5 MHz, DV1CK = 0)

SET

(P1).3

;

P13 output latch

← 1

(P1CR), 00001000B

;

Configures P13 as an output mode

(TBTCR), 10000000B

;

DVOEN

← 1, DVOCK ← 00

Table 2.5.1 Divider Output Frequency (Example: at fc

= 12.5 MHz, fs = 32.8 kHz)

Divider Output Frequency [kHz]

NORMAL1/2, IDLE1/2 MODE

DV7CK

= 0

DV7CK

= 1

DVOCK

DV1CK

= 0

DV1CK

= 1

DV1CK

= 0

DV1CK

= 1

SLOW, SLEEP

Mode

1.526 k

3.502

6.104

12.207

0.763 k

1.526

3.502

6.104

1.024 k

2.048

4.096

8.192

1.024 k

2.048

4.096

8.192

1.024 k

2.048

4.096

8.192

Figure 2.5.2 Divider Output

Data output

Output latch

P13 ( DVO )

Selector

D Q

fc/2

13, fc/214 or fs/25

fc/2

12 ,fc/213 or fs/24

fc/2

11 ,fc/212 or fs/23

fc/2

10 ,fc/211 or fs/22

DVOCK

DVOEN

DVOCK

Divider output control register

(a) Configuration of divider output circuit

(b) Divider output timing chart

P13 output latch

DVOEN

DVO

pin output

Output enable (P1CR3)

2007-10-19

TMP88CU74F Datasheet(PDF) 59 Page - Toshiba Semiconductor

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